Low-power warp processor for power efficient high-performance embedded systems

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2007, Pages 141-146

  Lysecky, Roman ^a  

^a University of Arizona

Author keywords

Dynamically adaptable systems; Embedded systems; Hardware software partitioning; Low power; Warp processing

Indexed keywords

COMPUTER SIMULATION; EMBEDDED SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); LOGIC DESIGN; OPTIMIZATION;

DYNAMICALLY ADAPTABLE SYSTEMS; SOFTWARE PARTITIONING; WARP PROCESSING;

PROGRAM PROCESSORS;

EID: 34548312071     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2007.364581     Document Type: Conference Paper

References (23)

1. Berkeley Design Technology, Inc. http://www.bdti.eom/articles/ info_eet0207fpga.htm#DSPEnhanced%20FPGAs. 2004.
2. Böhm, W., Hammes, J., Draper, B., Chawathe, M., Ross, C., Rinker, R., Najjar, W. Mapping a Single Assignment Programming Language to Reconfigurable Systems. Journal of Supercomputing, Vol. 21, pp. 117-130, 2002.
3. Burger, D., T. Austin. The SimpleScalar Tool Set, version 2.0. SIGARCH Computer Architecture News, 1997.
4. EEMBC. Embedded Microprocessor Benchmark Consortium, http://www.eembc. org, 2005.
5. Ernst, R., J. Henkel, T. Benner. Hardware-Software Cosynthesis for Microcontrollers. IEEE Design & Test of Computers, Oct/Dec, pp. 64-75, 1993.
6. Gordon-Ross, A., F. Vahid. Frequent Loop Detection Using Efficient Non-Intrusive On-Chip Hardware. Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), pp. 117-124, 2003.
7. Guo, Z., Buyukkurt, B., Najjar, W., Vissers, K. Optimized Generation of Data-Path from C Codes. Design Automation and Test in Europe Conference (DATE), pp. 112-117, 2005.
8. Henkel, J. A Low Power Hardware/Software Partitioning Approach for Core-based Embedded Systems. Design Automation Conference, pp. 122-127, 1999.
9. Intel Corp. XScale PXA27x Processor Family. http://www.intel.com/design/ pca/prodbref/253820.htm, 2006.
10. Keane, J., C. Bradley, C. Ebeling. A Compiled Accelerator for Biological Cell Signaling Simulations. International Symposium on Field-Programmable Gate Arrays (FPGA), pp. 233-241, 2004.
11. Lee, C., M. Potkonjak, W. Mangione-Smith. MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems. International Symposium on Microarchitecture (MICRO), pp. 330-335, 1997.
12. Lysecky, R., G. Stitt, F. Vahid. Warp Processors. ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 11, No. 3, pp. 659-681, 2006.
13. Lysecky, R., F. Vahid. On-chip Logic Minimization. Design Automation Conference (DAC), pp. 334-337, 2003.
14. Lysecky, R., F. Vahid, S. Tan. Dynamic FPGA Routing for Just-in-Time FPGA Compilation. Design Automation Conference (DAC), pp. 954-959, 2004.
15. Malik, A., B. Moyer, D. Cermak. A Low Power Unified Cache Architecture Providing Power and Performance Flexibility. International Symposium on Low Power Electronics and Design (ISLPED), pp. 241-243, 2000.
16. Memik, G., W. Mangione-Smith, W. Hu. NetBench: A Benchmarking Suite for Network Processors. International Conference on Computer-Aided Design (ICCAD), 2001.
17. Stitt, G., F. Vahid. The Energy Advantages of Microprocessor Platforms with On-Chip Configurable Logic. IEEE Design and Test of Computers, Nov/Dec 2002.
18. Stitt, G., F. Vahid. New Decompilation Techniques for Binary-level Co-processor Generation. International Conference on Computer Aided Design (ICCAD), 2005.
19. Stitt, G., F. Vahid, G. McGregor, B. Einloth. Hardware/Software Partitioning of Software Binaries: A Case Study of H.264 Decode. International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), pp. 285-290, 2005.
20. Stitt, G., F. Vahid, S. Nematbakhsh. Power Savings and Speedups from Partitioning Critical Loops to Hardware in Embedded Systems. ACM Transactions on Embedded Computing Systems (TECS), Vol. 3, No. 1, pp. 218-232, 2004.
21. Tuan, T., S. Kao, A. Rahman, S. Das, S. Trimberger. A 90nm Low-Power FPGA for Battery-Powered Applications. International Symposium of Field Programmable Gate Arrays (FPGA), 2006.
22. Venkataramani, G., W. Najjar, F. Kurdahi, N. Bagherzadeh, W. Bohm. A Compiler Framework for Mapping Applications to a Coarse-grained Reconfigurable Computer Architecture. Conf. on Compiler, Architecture and Synthesis for Embedded Systems (CASES), 2001.
23. Wan, M., Y. Ichikawa, D. Lidsky, L. Rabaey. An Power Conscious Methodology for Early Design Space Exploration of Heterogeneous DSPs. ISSS Custom Integrated Circuits Conference (CICC), 1998.