Capacitive coupling noise in high-speed VLSI circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 24, Issue 3, 2005, Pages 478-488

  Heydari, Payam ^a   Pedram, Massoud ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b University of Southern California   (United States)

Author keywords

Capacitance; CMOS circuits; Crosstalk; Deep submicron; Interconnect; Noise; Very large scale integration (VLSI)

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; CROSSTALK; ERROR ANALYSIS; ESTIMATION; MATHEMATICAL MODELS; PARAMETER ESTIMATION; SPURIOUS SIGNAL NOISE; TIME DOMAIN ANALYSIS;

DEEP SUBMICRON; HIGH SPEED INTEGRATED CIRCUITS; INTERCONNECT; NOISE;

VLSI CIRCUITS;

EID: 15244352750     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2004.842798     Document Type: Article

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