An alpha immune and ultra low neutron SER high density SRAM

Annual Proceedings - Reliability Physics (Symposium)

Volumn , Issue , 2004, Pages 671-672

  Roche, Philippe ^a   Jacquet, François ^a   Caillat, Christian ^a   Schoellkopf, Jean Pierre ^a  

^a STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; DIELECTRIC MATERIALS; DYNAMIC RANDOM ACCESS STORAGE; FLIP FLOP CIRCUITS; IONIZING RADIATION; MONTE CARLO METHODS; NEUTRON ABSORPTION; ROBUSTNESS (CONTROL SYSTEMS);

ERROR CODE CORRECTION (ECC); LOGIC HARDNING; SOFT ERROR RATE (SER);

STATIC RANDOM ACCESS STORAGE;

EID: 3042658177     PISSN: 00999512     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. P.Roche et al., "Comparisons of Soft Error Rate for SRAMs in Commercial SOI and Bulk below the 130 nm Technology Node", IEEE Trans. Nucl. Sci., vol. 40, Dec. 2003.
2. R. Baumann, "SER tutorial", Proceeding IEDM 2001.
3. JEDEC standard n° JESD89, www.jedec.org.
4. J.Stinson et al., "A l.5GHz Third Generation Itanium Processor", Proceeding ISSCC 2003, February 2003.