Reliable GALS implementation of MPEG-4 encoder with mixed clock FIFO on standard FPGA

Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL

Volumn , Issue , 2006, Pages 495-500

  Kulmala, Ari ^a   Hämäläinen, Timo D ^a   Hännikäinen, Marko ^a  

^a TAMPERE UNIVERSITY OF TECHNOLOGY   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CLOCKS; ELECTRIC POWER SUPPLIES TO APPARATUS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FUZZY LOGIC; INTEGRATED CIRCUITS; MOTION PICTURE EXPERTS GROUP STANDARDS; PRODUCT DEVELOPMENT; PROGRAMMABLE LOGIC CONTROLLERS; STANDARDS;

AREA OVERHEAD; ASIC DESIGNS; COMPLEXITY MANAGEMENT; CUSTOM DEVELOPMENT; DESIGN ITERATIONS; DESIGN TIME; FIELD PROGRAMMABLE LOGIC (FPL); FPGA PLATFORMS; GLOBALLY ASYNCHRONOUS LOCALLY SYNCHRONOUS (GALS); INTERNATIONAL CONFERENCES; KEY BUILDING BLOCK; LARGE SYSTEMS; MIXED CLOCK FIFO; MPEG-4 VIDEO; STANDARD DEVELOPMENT;

STANDARDIZATION;

EID: 38149077629     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2006.311257     Document Type: Conference Paper

References (12)

1. A. Iyer and D. Marculescu, "Power and Performance Evaluation of Globally Asynchronous Locally Synchronous Processors ", Proc. 29th Annual International Symposium on Computer Architecture, IEEE, 25-29 May 2002, pp. 158-168.
2. Salminen, E., Lahtinen, V., Kangas, T., Riihimäki, J., Kuusilinna, K., and Hämäläinen, T. D., "HIBI v.2 Communication Network for System-on-Chip", LNCS 3133 Computer Systems: Architectures, Modeling, and Simulation. A.D. Pimentel, S. Vassiliadis, (eds.). Springer-Verlag, Berlin, Germany, July 2004, pp. 412-422.
3. E. Brunvand, "Low Latency Self-Timed Flow-Through FIFOs", Proc. Sixteenth Conference on Advanced Research in VLSI, IEEE, 27-29 March 1995, pp. 76-90.
4. J.T. Yantchev, C.G. Huang, M.B. Josephs, and I.M. Nedelchev, "Low-Latency Asynchronous FIFO Buffers", Proc. Second Working Conference on Asynchronous Design Methodologies, IEEE, 30-31 May 1995, pp. 24-31.
5. I. Sutherland and S. Fairbanks, "GasP: A Minimal FIFO Control", Seventh International Symposium on Asynchronous Circuits and Systems, IEEE, 11-14 March 2001, pp. 46-53.
6. T. Chelcea and S.M Nowick, "A Low-Latency FIFO for Mixed-Clock Systems", Proc. IEEE Computer Society Workshop on VLSI, IEEE, 27-28 April 2000, pp. 119-126.
7. Q.T. Ho, J-B. Rigaud, L. Fesquet, M. Renaudin, and R. Rolland, "Implementing Asynchronous Circuits on LUT Based FPGAs", Proc. 12th International Conference on Field-Programmable Logic and Applications, Springer-Verlag, September 2-4 2002, pp. 36-46.
8. J. Quartana, S. Renane, A. Baixas, L. Fesquet, and M. Renaudin, "GALS System Prototyping Using Multiclock FPGAs and Asynchronous Network-on-Chips", Proc. International Conference on Field Programmable Logic and Applications, IEEE, 24-26 August 2005, pp. 299-304.
9. R. Dobkin, R. Ginosar, and C.P. Sotiriou, "Data Synchronization Issues in GALS SoCs", Proc. 10th International Symposium on Asynchronous Circuits and Systems, IEEE, 2004, pp. 170-179.
10. R. Ginosar, "Fourteen Ways to Fool Your Synchronizer", Proc. Ninth International Symposium on Asynchronous Circuits and Systems, IEEE, 12-15 May 2003, pp. 89-96.
11. E. Salminen, A. Kulmala, and T.D. Hämäläinen, "HIBI-based Multiprocessor SoC on FPGA", Proc. IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, 23-26 May 2005, pp. 3351-3354.
12. O. Lehtoranta, E. Salminen, A. Kulmala, M. Hännikäinen, and T.D. Hämäläinen, "A parallel MPEG-4 encoder for FPGA based multiprocessor SoC", Proc. International Conference on Field Programmable Logic and Applications, IEEE, 24-26 August 2005, pp. 380-385.