메뉴 건너뛰기




Volumn 3133, Issue , 2004, Pages 413-422

HIBI v.2 communication network for system-on-chip

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; COMPLEX NETWORKS; DATA TRANSFER; DISTRIBUTED COMPUTER SYSTEMS; ENERGY CONSERVATION; MICROPROCESSOR CHIPS; NETWORK ARCHITECTURE; NETWORK-ON-CHIP; PROGRAMMABLE LOGIC CONTROLLERS; QUALITY OF SERVICE; VLSI CIRCUITS;

EID: 33845310973     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-27776-7_43     Document Type: Article
Times cited : (12)

References (24)
  • 1
    • 0003840779 scopus 로고    scopus 로고
    • Kluwer Academic Publishers, Norwell, MA
    • Chang, H. et al.: Surviving SoC Revolution. Kluwer Academic Publishers, Norwell, MA (1999)
    • (1999) Surviving SoC Revolution
    • Chang, H.1
  • 4
    • 0034428118 scopus 로고    scopus 로고
    • System-Level Design: Orthogonalization of Concerns and Platform-Based Design
    • Keutzer, K., et al.: System-Level Design: Orthogonalization of Concerns and Platform-Based Design. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 19, issue 12 (2000) 1523-1543
    • (2000) IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems , vol.19 , Issue.12 , pp. 1523-1543
    • Keutzer, K.1
  • 7
    • 0346206710 scopus 로고
    • Zalewski, J. (ed.): IEEE Computer Society Press, Los Alamitos, CA
    • Zalewski, J. (ed.): Advanced Multiprocessor Bus Architectures. IEEE Computer Society Press, Los Alamitos, CA (1995)
    • (1995) Advanced Multiprocessor Bus Architectures
  • 9
    • 0035444259 scopus 로고    scopus 로고
    • Viper: A Multiprocessor SoC for Advanced Set-Top Box and Digital TV Systems
    • Dutta, S., et al.: Viper: A Multiprocessor SoC for Advanced Set-Top Box and Digital TV Systems. IEEE Design and Test of Computers, vol. 18, issue 5 (2001) 21-31
    • (2001) IEEE Design and Test of Computers , vol.18 , Issue.5 , pp. 21-31
    • Dutta, S.1
  • 12
    • 0036294704 scopus 로고    scopus 로고
    • Overview of Bus-based System-On-Chip Interconnections
    • Salminen, E., et al.: Overview of Bus-based System-On-Chip Interconnections. In proc. ISCAS (2002) II-372-II-375.
    • (2002) Proc. ISCAS
    • Salminen, E.1
  • 13
    • 0036149420 scopus 로고    scopus 로고
    • Networks on chips: A New SoC Paradigm
    • Benini, L., de Micheli, G.: Networks on chips: A New SoC Paradigm. Computer, vol. 35, issue 1 (2002) 70-78
    • (2002) Computer , vol.35 , Issue.1 , pp. 70-78
    • Benini, L.1    De Micheli, G.2
  • 14
    • 0042111484 scopus 로고    scopus 로고
    • Jantsch, A., Tenhunen, H. (eds.): Kluwer Academic Publishers, Dordrecht, The Netherlands
    • Jantsch, A., Tenhunen, H. (eds.): Networks on Chip. Kluwer Academic Publishers, Dordrecht, The Netherlands (2003)
    • (2003) Networks on Chip
  • 15
    • 9544232495 scopus 로고    scopus 로고
    • A Low Area Overhead Packet-Switched Network on Chip: Architecture and Prototyping
    • Moraes, F., et al.: A Low Area Overhead Packet-Switched Network on Chip: Architecture and Prototyping. In proc. IFIP VLSI-SOC (2003) 174-179
    • (2003) Proc. IFIP VLSI-SOC , pp. 174-179
    • Moraes, F.1
  • 16
    • 0345358582 scopus 로고    scopus 로고
    • Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Network on Chip (Extended version)
    • Rijpkema, E., et al.: Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Network on Chip (Extended version). IEEE Proc. Computers and Digital Techniques, vol 150, issue 5 (2003) 294-302
    • (2003) IEEE Proc. Computers and Digital Techniques , vol.150 , Issue.5 , pp. 294-302
    • Rijpkema, E.1
  • 17
    • 9544220632 scopus 로고    scopus 로고
    • Micro-network for SoC: Implementation of 32-port SPIN Network
    • Andriahatenenaina, A., Greiner, A.: Micro-network for SoC: Implementation of 32-port SPIN Network. In proc. DATE (2003) 11128-11129
    • (2003) Proc. DATE , pp. 11128-11129
    • Andriahatenenaina, A.1    Greiner, A.2
  • 18
    • 35048817000 scopus 로고    scopus 로고
    • An Autonomous Error-tolerant Cell for Scalable Network-on-Chip Architectures
    • Valtonen, T., et al.: An Autonomous Error-tolerant Cell for Scalable Network-on-Chip Architectures. In proc. Norchip (2001) 198-203
    • (2001) Proc. Norchip , pp. 198-203
    • Valtonen, T.1
  • 19
    • 34548342553 scopus 로고    scopus 로고
    • A Study on Communication Issues for System-on-Chip
    • Zeferino, C.A., et. al.: A Study on Communication Issues for System-on-Chip. In proc. SBCCI (2002) 121-126
    • (2002) Proc. SBCCI , pp. 121-126
    • Zeferino, C.A.1
  • 20
    • 0002665957 scopus 로고    scopus 로고
    • Low-Latency Interconnection for IP-Block Based Multimedia Chips
    • Kuusilinna, K., et al.: Low-Latency Interconnection for IP-Block Based Multimedia Chips. In proc. PDCN (1998) 411-416
    • (1998) Proc. PDCN , pp. 411-416
    • Kuusilinna, K.1
  • 21
    • 0037029241 scopus 로고    scopus 로고
    • Interconnection scheme for continuous-media systems-on-chip
    • Lahtinen. V., et al.: Interconnection scheme for continuous-media systems-on-chip. Microprocessors and Microsystems vol. 26, issue 3 (2002) 123-138
    • (2002) Microprocessors and Microsystems , vol.26 , Issue.3 , pp. 123-138
    • Lahtinen, V.1
  • 23
    • 33744723974 scopus 로고    scopus 로고
    • System-on-Chip Communication Optimization with Bus Monitoring
    • Kangas, T., et al.: System-on-Chip Communication Optimization with Bus Monitoring. In proc. DDECS (2002) 304-309
    • (2002) Proc. DDECS , pp. 304-309
    • Kangas, T.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.