A parallel MPEG-4 encoder for FPGA based multiprocessor SOC

Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL

Volumn 2005, Issue , 2005, Pages 380-385

  Lehtoranta, Olli ^a   Salminen, Erno ^a   Kulmala, Ari ^a   Hännikäinen, Marko ^a   Hämäläinen, Timo D ^a  

^a TAMPERE UNIVERSITY OF TECHNOLOGY   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; CRYPTOGRAPHY; DATA PROCESSING; FIELD PROGRAMMABLE GATE ARRAYS; PARALLEL PROCESSING SYSTEMS; STORAGE ALLOCATION (COMPUTER);

MULTIPROCESSOR; SLICE CODING; SPATIAL PARALLELIZATION; SYSTEM-ON-CHIP (SOC);

INTERCONNECTION NETWORKS;

EID: 33744724112     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2005.1515751     Document Type: Conference Paper

References (11)

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4. M. Garrido, et al., "An FPGA Implementation of a Flexible Architecture for H.263 Video Coding," IEEE Transactions on Consumer Electronics, vol. 48, no. 4, pp. 1056-1066, Nov. 2002.
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9. E. Salminen, et al., "HIBI v.2 Communication Network for System-on-Chip," In Pimentel, A.D., Vassiliadis, S. (eds.): LNCS 3133 Computer Systems: Architectures, Modeling, and Simulation, Springer-Verlag, Berlin, pp. 412-422, 2004.
10. O. Lehtoranta, et al., "Parallel Implementation of Video Encoder on Quad DSP System," Elsevier Microprocessors and Microsystems, vol. 26, issue 1, pp. 1-15, 2002.
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