A robust embedded ladder-oxide/Cu multilevel interconnect technology for 0.13 μm complementary metal oxide semiconductor generation

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 46, Issue 3 A, 2007, Pages 954-961

  Oda, Noriaki ^a,b   Ito, Shinya ^a   Takewaki, Toshiyuki ^a   Shiba, Kazutoshi ^a   Kunishima, Hiroyuki ^a   Hironaga, Nobuo ^a   Honma, Ichiro ^a   Nanba, Hiroaki ^a   Yokogawa, Shinji ^a   Kameyama, Akiko ^a   Goto, Takayuki ^a,c   Usami, Tatsuya ^a   Ohto, Koichi ^a   Kubo, Akira ^a   Suzuki, Mieko ^a   Yamamoto, Yoshiaki ^a,d   Watanabe, Susumu ^a   Yamada, Kenta ^a   Ikeda, Masahiro ^a   Ueno, Kazuyoshi ^a,e   Horiuchi, Tadahiko ^a,f   more..

^a RENESAS TECHNOLOGY CORP   (Japan)

^b SEMICONDUCTOR LEADING EDGE TECHNOLOGIES INC   (Japan)

^c NEC CORPORATION   (Japan)

^d NEC Corporation of America   (United States)

^e SHIBAURA INSTITUTE OF TECHNOLOGY   (Japan)

^f NSCore Inc   (Japan)

Author keywords

0.13 m node; CMOS; Complementary metal oxide semiconductor; Copper plug; Cu interconnect; Ladder oxide; Low k; Single damascene

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COPPER; ELECTRIC BREAKDOWN; ELECTROMIGRATION; METALLIZING;

COPPER PLUG; CU INTERCONNECT; LADDER-OXIDE; SINGLE DAMASCENE;

OPTICAL INTERCONNECTS;

EID: 34547885443     PISSN: 00214922     EISSN: 13474065     Source Type: Journal    
DOI: 10.1143/JJAP.46.954     Document Type: Article

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