Stress relaxation in dual-damascene Cu interconnects to suppress stress-induced voiding

Proceedings of the IEEE 2003 International Interconnect Technology Conference, IITC 2003

Volumn , Issue , 2003, Pages 210-212

  Kawano, M ^a   Fukase, T ^a   Yamamoto, Y ^a   Ito, T ^a   Yokogawa, S ^a   Tsuda, H ^a   Kunimune, Y ^a   Saitoh, T ^a   Ueno, K ^a   Sekine, M ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

Dielectrics; Failure analysis; Finite element methods; High temperature superconductors; Indium tin oxide; National electric code; Shape; Temperature dependence; Tensile stress; Testing

Indexed keywords

DIELECTRIC MATERIALS; FINITE ELEMENT METHOD; HIGH TEMPERATURE SUPERCONDUCTORS; INTEGRATED CIRCUIT INTERCONNECTS; OXIDE SUPERCONDUCTORS; STRESS ANALYSIS; STRESS RELAXATION; TEMPERATURE DISTRIBUTION; TENSILE STRESS; TENSILE TESTING; TESTING; TIN OXIDES;

3D FINITE ELEMENT METHOD (FEM); DIELECTRIC STRUCTURE; INDIUM TIN OXIDE; NATIONAL ELECTRIC CODE; SHAPE; STRESS-INDUCED FAILURES; STRESS-INDUCED VOIDING; TEMPERATURE DEPENDENCE;

FAILURE ANALYSIS;

EID: 28744446852     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2003.1219756     Document Type: Conference Paper

References (8)

1. E. Ogawa, et al., "Stress-induced voiding under vias connected to wide Cu metal leads" Proc. of IRPS (2002) pp. 312-321.
2. K. Yoshida, et al., "Stress-induced voiding phenomena for an actual CMOS LSI interconnects" Proc. of IEDM (2002) pp. 753-756.
3. T. Otsuka, and A. Yamagami, Japan Patent App. No. 113286 (2000).
4. T. Oshima, et al., "Improvement of thermal stability of via resistance in dual damascene copper interconnection" Proc. of IEDM (2000) pp. 123 126.
5. T. Oshima, et al., "Suppression of stress-induced voiding in copper interconnects" Proc. of IEDM (2002) pp. 757-760.
6. M. Ueki, et al., "Suppression of stress induced open failures between via and Cu wide line by inserting Ti layer under Ta/TaN barrier" Proc. of IEDM (2002) pp.749-752.
7. T. Saitoh, M. Kawano, and K. Ueno, "3-dimensional elastic-plastic finite element analysis of stress-induced voiding in Cu damascene interconnects of ultra-large-scale integrated circuits" (in Japanese), unpublished.
8. N. Oda, et al., "A robust embedded ladder-oxide/Cu multilevel interconnect technology for 0.13μm CMOS generation", Symp. on VLSI Tech. (2002) pp.34-35.