-
2
-
-
8744233904
-
Reconfigurable hardware SAT solvers: a survey of systems
-
Skliarova I., and Ferrari A.B. Reconfigurable hardware SAT solvers: a survey of systems. IEEE Trans. Comput. 53 11 (2004) 1449-1461
-
(2004)
IEEE Trans. Comput.
, vol.53
, Issue.11
, pp. 1449-1461
-
-
Skliarova, I.1
Ferrari, A.B.2
-
3
-
-
0035505389
-
An energy-efficient reconfigurable public-key cryptograph processor
-
Goodman J., and Chandrakasan A.P. An energy-efficient reconfigurable public-key cryptograph processor. IEEE J. Solid-State Circ. 36 11 (2001) 1808-1820
-
(2001)
IEEE J. Solid-State Circ.
, vol.36
, Issue.11
, pp. 1808-1820
-
-
Goodman, J.1
Chandrakasan, A.P.2
-
4
-
-
34547751900
-
-
Xilinx Inc., Virtex-5 multi-platform FPGA overview. (22.01.07).
-
-
-
-
5
-
-
34547745959
-
-
® III FPGA family overview. (22.01.07).
-
-
-
-
6
-
-
34547790279
-
-
PACT XPP technologies, XPP products overview. (22.01.07).
-
-
-
-
7
-
-
34547803203
-
-
QuickSilver Technologies, Adapt2000 ACM system platform overview, (22.01.07).
-
-
-
-
8
-
-
34547772159
-
-
Triscend, A7 Field Configurable System-on-Chip datasheets, 2004. .
-
-
-
-
9
-
-
34547793095
-
-
Motorola, press release of MRC6011 RCF device, 2003. .
-
-
-
-
10
-
-
0000227930
-
Reconfigurable computing: a survey of systems and software
-
Compton K. Reconfigurable computing: a survey of systems and software. ACM Comput. Surv. 34 2 (2002) 171-210
-
(2002)
ACM Comput. Surv.
, vol.34
, Issue.2
, pp. 171-210
-
-
Compton, K.1
-
11
-
-
14844339402
-
-
K. Compton, J. Cooley, S. Knol, S. Hauck, Configuration relocation and defragmentation for reconfigurable computing, in: Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines (FCCM), 2000, pp. 279-280.
-
-
-
-
12
-
-
0036625327
-
Configuration relocation and defragmentation for run-time reconfigurable computing
-
Compton K., Li Z., Cooley J., Knol S., and Hauck S. Configuration relocation and defragmentation for run-time reconfigurable computing. IEEE Trans. VLSI Syst. 10 3 (2002) 209-220
-
(2002)
IEEE Trans. VLSI Syst.
, vol.10
, Issue.3
, pp. 209-220
-
-
Compton, K.1
Li, Z.2
Cooley, J.3
Knol, S.4
Hauck, S.5
-
13
-
-
84949186062
-
-
G. Brebner, O. Diessel, Chip-based reconfigurable task management, in: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 2001, pp. 182-191.
-
-
-
-
14
-
-
34547775811
-
-
Xilinx Inc., Application note XAPP290: Two flows for partial reconfiguration, module based or difference based. (22.01.07).
-
-
-
-
15
-
-
34547745442
-
-
Z. Li, Configuration management techniques for reconfigurable computing, PhD Thesis, Dept. of ECE, Northwestern University, 2002.
-
-
-
-
16
-
-
34047124293
-
-
Y. Qu, J.-P. Soininen, J. Nurmi, A parallel configuration model for reducing the run-time reconfiguration overhead, in: Proceedings of the Design Automation and Test in Europe Conference (DATE), 2006, pp. 965-970.
-
-
-
-
17
-
-
50049092233
-
Using constraint programming to achieve optimal prefetch scheduling for dependent tasks on run-time reconfigurable devices
-
Qu Y., Soininen J.-P., and Nurmi J. Using constraint programming to achieve optimal prefetch scheduling for dependent tasks on run-time reconfigurable devices. IEEE Int. Symp. System-on-Chip (2006) 83-86
-
(2006)
IEEE Int. Symp. System-on-Chip
, pp. 83-86
-
-
Qu, Y.1
Soininen, J.-P.2
Nurmi, J.3
-
18
-
-
34547798519
-
-
Atmel Corp., FPSLIC (AVR with FPGA). (22.01.07).
-
-
-
-
19
-
-
0034187952
-
MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications
-
Singh H., Lee M.-H., Lu G., Bagherzadeh N., Kurdahi F.J., and Chaves Filho E.M. MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications. IEEE Trans. Comput. 49 5 (2000) 465-481
-
(2000)
IEEE Trans. Comput.
, vol.49
, Issue.5
, pp. 465-481
-
-
Singh, H.1
Lee, M.-H.2
Lu, G.3
Bagherzadeh, N.4
Kurdahi, F.J.5
Chaves Filho, E.M.6
-
20
-
-
0141876846
-
A dynamically reconfigurable logic engine with a multi-context/multi-mode unified-cell architecture
-
Fujii T., et al. A dynamically reconfigurable logic engine with a multi-context/multi-mode unified-cell architecture. Proc. Int. Solid-State Circ. Conf. (1999) 360-361
-
(1999)
Proc. Int. Solid-State Circ. Conf.
, pp. 360-361
-
-
Fujii, T.1
-
21
-
-
84957892243
-
-
O. Diessel, H. ElGindy, Run-time compaction of FPGA designs, in: Proceedings of the Field-Programmable Logic and Applications (FPL), 1997, pp. 131-140.
-
-
-
-
22
-
-
0034187808
-
Dynamic scheduling of tasks on partially reconfigurable FPGAs
-
Diessel O., ElGindy H., Middendorf M., Schmeck H., and Schmidt B. Dynamic scheduling of tasks on partially reconfigurable FPGAs. IEE Proc. Comput. Digital Tech. 147 3 (2000) 181-188
-
(2000)
IEE Proc. Comput. Digital Tech.
, vol.147
, Issue.3
, pp. 181-188
-
-
Diessel, O.1
ElGindy, H.2
Middendorf, M.3
Schmeck, H.4
Schmidt, B.5
-
24
-
-
34547781227
-
-
H. Walder, M. Platzner, Non-preemptive multitasking on FPGAs: task placement and footprint transform, in: Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2002, pp. 24-30.
-
-
-
-
25
-
-
8744312724
-
Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks
-
Steiger C., Walder H., and Platzner M. Operating systems for reconfigurable embedded platforms: online scheduling of real-time tasks. IEEE Trans. Comput. 53 11 (2004) 1393-1407
-
(2004)
IEEE Trans. Comput.
, vol.53
, Issue.11
, pp. 1393-1407
-
-
Steiger, C.1
Walder, H.2
Platzner, M.3
-
26
-
-
35048895284
-
-
J. Tabero, J. Septién, H. Mecha, D. Mozos, A low fragmentation heuristic for task placement in 2D RTR HW management, in: Proceedings of the Field-Programmable Logic and Applications (FPL), 2004, pp. 241-250.
-
-
-
-
27
-
-
3042662324
-
-
G. Chen, M. Kandemir, U. Sezer, Configuration sensitive process scheduling for FPGA-based computing platforms, in: Proceedings of the Design Automation and Test in Europe Conference (DATE), 2004, pp. 486-493.
-
-
-
-
28
-
-
0031643963
-
Configuration prefetch for single context reconfigurable coprocessors
-
Hauck S. Configuration prefetch for single context reconfigurable coprocessors. ACM Symp. FPGA (1998) 65-74
-
(1998)
ACM Symp. FPGA
, pp. 65-74
-
-
Hauck, S.1
-
29
-
-
33646940730
-
-
J. Resano, D. Mozos, F. Catthoor, A hybrid prefetch scheduling heuristic to minimize at run-time the reconfiguration overhead of DRHW, in: Proceedings of the Design Automation and Test in Europe Conference (DATE), 2005, pp. 106-111.
-
-
-
-
30
-
-
34547735513
-
-
S. Li, N.K. Jha, Hardware-software co-synthesis of low power real-time distributed embedded systems with dynamically reconfigurable FPGAs, in: Proceedings of the International Conference on VLSI Design, 2002, pp. 245-254.
-
-
-
-
31
-
-
24944568059
-
-
E.M. Panainte, K. Bertels, S. Vassiliadis, Instruction scheduling for dynamic hardware reconfiguration, in: Proceedings of the Design Automation and Test in Europe Conference (DATE), 2005, pp. 100-105.
-
-
-
-
32
-
-
8744241430
-
The Molen polymorphic processor
-
Vassiliadis S., Wong S., Gaydadjiev G.N., Bertels K., Kuzmanov G., and Panainte E.M. The Molen polymorphic processor. IEEE Trans. Comput. 53 11 (2004) 1363-1375
-
(2004)
IEEE Trans. Comput.
, vol.53
, Issue.11
, pp. 1363-1375
-
-
Vassiliadis, S.1
Wong, S.2
Gaydadjiev, G.N.3
Bertels, K.4
Kuzmanov, G.5
Panainte, E.M.6
-
33
-
-
34047182144
-
-
E.M. Panainte, K. Bertels, S. Vassiliadis, Compiler driven FPGA-area allocation for reconfigurable computing, in: Proceedings of the Design Automation and Test in Europe Conference (DATE), 2006, pp. 369-374.
-
-
-
-
34
-
-
0035706050
-
A framework for reconfigurable computing: task scheduling and context management
-
Maestre R., Kurdahi F.J., Fernández M., Hermida R., Bagherzadeh N., and Singh H. A framework for reconfigurable computing: task scheduling and context management. IEEE Trans. VLSI Syst. 9 6 (2001)
-
(2001)
IEEE Trans. VLSI Syst.
, vol.9
, Issue.6
-
-
Maestre, R.1
Kurdahi, F.J.2
Fernández, M.3
Hermida, R.4
Bagherzadeh, N.5
Singh, H.6
-
35
-
-
0347117076
-
-
S.P. Fekete, E. Kohler, J. Teich, Optimal FPGA module placement with temporal precedence constraints, in: Proceedings of the Design Automation and Test in Europe Conference (DATE), 2001, pp. 658-665.
-
-
-
-
36
-
-
0012348359
-
In pursuit of the Holy Grail
-
Freuder E.C. In pursuit of the Holy Grail. Constraints 2 1 (1997) 57-61
-
(1997)
Constraints
, vol.2
, Issue.1
, pp. 57-61
-
-
Freuder, E.C.1
-
41
-
-
34547785054
-
-
SICS AB, SICSTUS manual. (22.01.07).
-
-
-
-
42
-
-
0031681657
-
-
R.P. Dick, D.L. Rhodes, W. Wolf, TGFF: task graphs for free, in: Proceedings of the International Workshop on HW/SW co-design, 1998, pp. 97-101.
-
-
-
|