A parallel configuration model for reducing the run-time reconfiguration overhead

Proceedings -Design, Automation and Test in Europe, DATE

Volumn 1, Issue , 2006, Pages

  Qu, Yang ^a   Soininen, Juha Pekka ^a   Nurmi, Jari ^b  

^a VTT TECHNICAL RESEARCH CENTRE OF FINLAND   (Finland)

^b TAMPERE UNIVERSITY OF TECHNOLOGY   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

FORMAL LOGIC; MULTITASKING; SILICON; STATIC RANDOM ACCESS STORAGE;

PARALLEL CONFIGURATION MODELS; PREFETCH SCHEDULING TECHNIQUE; RECONFIGURABLE LOGIC; SILICON REUSABILITY;

PARALLEL PROGRAMMING;

EID: 34047124293     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. H. Singh, et al, "MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications", IEEE Trans. Vol.49, No.5, pp.465-481, 2000.
2. S. Hauck, "Configuration Prefetch for Single Context Reconfigurable Coprocessors", ACM/SIGDA International Symposium on FPGA, pp. 65-74, 1998.
3. rd Norchip conference, pp. 86-89, 2005.
4. J. Resano, et al, "A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-Time the Reconfiguration Overhead of DRHW", DATE'05, pp. 106-111, 2005.
5. S. Li and N.K. Jha, "HW/SW Co-Synthesis of Low Power Real-Time Distributed Embedded Systems with Dynamically Reconfigurable FPGAs", ASP-DAC'02, pp. 345-352, 2002.
6. Xilinx, datasheet and application notes, www.xilinx.com.
7. O. Diessel, et al, "Dynamic scheduling of tasks on partially reconfigurable FPGAs", IEE Proc.-Comput. Digit Tech, Vol. 147, No. 3, pp. 181-188, 2000.
8. PACT XPP Technologies, "Reconfiguration White Paper", www.pactcorp.com.