TROY: Track router with yield-driven wire planning

Proceedings - Design Automation Conference

Volumn , Issue , 2007, Pages 55-58

  Cho, Minsik ^a   Xiang, Hua ^b   Puri, Ruchir ^b   Pan, David Z ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Manufacturability; Track routing; VLSI; Yield

Indexed keywords

MANUFACTURABILITY; PROBABILITY OF FAILURE (POF); SECOND ORDER CONIC PROGRAMMING (SOCP); TRACK ROUTING;

FAILURE ANALYSIS; HAMILTONIANS; OPTIMIZATION; PROBABILITY; VLSI CIRCUITS;

ELECTRIC WIRE;

EID: 34547335179     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2007.375124     Document Type: Conference Paper

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