Layout compaction for yield optimization via critical area minimization

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2000, Pages 122-125

  Bourai, Youcef ^a   Shi, C J Richard ^a  

^a UNIVERSITY OF WASHINGTON   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AREA MINIMIZATION; COMPACTION ALGORITHMS; EXTRA VARIABLES; IC LAYOUT; LAYOUT COMPACTION; MINIMIZATION PROBLEMS; SECOND PHASE; YIELD OPTIMIZATION;

COMPACTION; EXHIBITIONS; INTEGRATED CIRCUIT LAYOUT;

ALGORITHMS;

EID: 34547362783     PISSN: 15301591     EISSN: None     Source Type: Journal    
DOI: 10.1109/DATE.2000.840027     Document Type: Article

References (9)

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8. H. Xue, C. N. Di, and J. A. Jess, "Fast multi-layer critical area computation, " in Proc. of IEEE Int. Workshop on Defect and Fault tolerance on VLSI Systems. Oct. 1993.
9. H. Xue, C. N. Di, and J. A. Jess, "A net-oriented method for realistic fault analysis, " in Proc. IEEE Int. Conf. On Computer Aided-Design, pp. 78-84, Nov. 1993.