Timing- and crosstalk-driven area routing

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 20, Issue 4, 2001, Pages 528-544

  Tseng, Hsiao Ping ^a,b   Scheffer, Louis ^a,c   Sechen, Carl ^a,b  

^a IEEE   (United States)

^b University of Washington   (United States)

^c CADENCE DESIGN SYSTEMS   (United States)

Author keywords

Area routing; Crosstalk; Net order; Timing driven

Indexed keywords

CROSSTALK DRIVEN AREA ROUTING; ELMORE DELAY CALCULATOR; GEOMETRIC CONSTRAINTS; INTRALAYER COUPLING CAPACITANCE; TIMING DRIVEN AREA ROUTING; WIRE GEOMETRIC RATIO;

CAPACITANCE MEASUREMENT; COMPUTATIONAL GEOMETRY; CONSTRAINT THEORY; DELAY CIRCUITS; DESIGN FOR TESTABILITY; GLOBAL OPTIMIZATION; INTEGRATED CIRCUIT TESTING; PETRI NETS; SWITCHING CIRCUITS; TUNING;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0035306893     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.918211     Document Type: Article

References (22)