Targeted layout modifications for semiconductor yield/reliability enhancement

IEEE Transactions on Semiconductor Manufacturing

Volumn 17, Issue 4, 2004, Pages 573-581

  Allan, Gerard A ^a  

^a Predictions Software Ltd   (United Kingdom)

Author keywords

Critical area; Layout modification; Redundant via; Reliability; Semiconductor yield; Survey sampling; Track displacement; Wire spreading; Yield modeling

Indexed keywords

COMPUTER PROGRAMMING LANGUAGES; FABRICATION; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUITS; RELIABILITY; WIRE;

CRITICAL AREA; LAYOUR MODIFICATIONS; REDUNDANT VIA; SEMICONDUCTOR YIELD; SURVEY SAMPLING; TRACK DISPLACEMENT; WIRE SPREADING; YIELD MODELING;

SEMICONDUCTOR MATERIALS;

EID: 9144256265     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSM.2004.835727     Document Type: Article

References (19)

1. G. A. Allan, A. J. Walton, and R. J. Holwill, "A yield improvement technique for IC layout using local design rules," IEEE Trans. Comput.-Aided Design, vol. CAD-11, pp. 1355-1362, Nov. 1992.
2. V. K. R. Chiluvuri and I. Koren, "Layout-synthesis techniques for yield enhancement," IEEE Trans. Semiconduct. Manufact., vol. 8, pp. 178-187, May 1995.
3. G. A. Allan and A. J. Walton, "Automated redundant via placement for increased yield and reliability," in Proc. SPIE Symp. Microelectronic Manufacture, Austin, TX, Oct. 1997, pp. 114-125.
4. T. C. Brennan and Assigned to International Business Machines Corporation, "Method for adding redundant vias on VIST chips," U.S. Patent 6066179, Apr. 2003.
5. A. Brand, A. Haranahalli, N. Hsieh, Y. C. Lin, G. Sery, N. Stenton, B. J. Woo, S. Ahmed, M. Bohr, S. Thompson, and S. Yang, "Intel's 0.25 micron, 2.0 volts logic process technology," Intel Technol. J., 1998.
6. E. Bruls, "Quality and reliability impact of defect data analysis," IEEE Trans. Semiconduct. Manufact., vol. 8, pp. 121-129, May 1995.
7. G. A. Allan and A. J. Walton, "Hierarchical critical area extraction with the EYE tool," in Proc. IEEE Workshop Defect Fault Tolerance in VLSI Systems, Lafayette, LA, Nov. 1995, pp. 28-36.
8. C. H. Stapper and R. J. Rosner, "Integrated circuit yield management and yield analysis: Development and implementation," IEEE Trans. Semiconduct. Manufact., vol. 8, no. 2, pp. 95-102, May 1995.
9. W. Maly and J. Deszczka, "Yield estimation model for VLSI artwork evaluation," Electron. Lett., vol. 19, no. 6, pp. 226-227, Mar. 1983.
10. D. M. H. Walker, Yield Simulation for Integrated Circuits, ser. International series in engineering and computer science. Boston, MA: Kluwer, 1987.
11. G. A. Allan and A. J. Walton, "Efficient extra material critical area algorithms," IEEE Trans. Comput.-Aided Design, vol. 18, pp. 1480-1486, Oct. 1999.
12. G. A. Allan, "Yield prediction by sampling IC layout," IEEE Trans. Comput.-Aided Design, vol. 19, pp. 359-371, Mar. 2000.
13. _, "Property estimation of an integrated circuit," U.S. Patent 6066179, May 2000.
14. G. A. Allan and A. J. Walton, "Yield prediction by sampling with the EYES tool," in Proc. IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems, Boston, MA, Nov. 1996, pp. 39-47.
15. EYES: User Manual, Predictions Software Ltd., Edinburgh, U.K., 2004.
16. S. Levasseur and F. Duvivier, "Application of a yield model merging critical areas and defectivity data to industrial products," in Proc. IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems, Paris, France, Oct. 1997, pp. 11-19.
17. S. Barberan and F. Duvivier, "Management of critical areas and defective data for yield trend modeling," in Proc. IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems, Austin, TX, Nov. 1998, pp. 17-25.
18. G. A. Allan and A. J. Walton, "Critical area extraction for soft fault estimation," IEEE Trans. Semiconduct. Manufact., vol. 11, no. 1, pp. 146-154, Feb. 1998.
19. C. H. Stapper, "Modeling of integrated circuit defect sensitivities," IBM J. Res. Develop., vol. 27, no. 6, pp. 549-557, Nov. 1983.