Quadratic placement for 3D circuits using Z-Cell shifting, 3D iterative refinement and simulated annealing

SBCCI 2006 - 19th Symposium on Integrated Circuits and Systems Design

Volumn 2006, Issue , 2006, Pages 220-225

  Hentschke, Renato ^a   Flach, Guilherme ^a   Pinto, Felipe ^a   Reis, Ricardo ^a  

^a FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

3D circuits; Cell shifting; Placement; Quadratic placement

Indexed keywords

ALGORITHMS; ITERATIVE METHODS; QUADRATIC PROGRAMMING; SIMULATED ANNEALING;

3D ITERATIVE REFINEMENT; CELL SHIFTING; QUADRATIC PLACEMENT;

NETWORKS (CIRCUITS);

EID: 33750919241     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1150343.1150399     Document Type: Conference Paper

References (21)

1. C. Ababei, Y. Feng, B. Goplen, H. Mogal, T. Zhang, K. Bazargan and S. Sapatnekar. Placement and Routing in 3D Integrated Circuits. IEEE Design and Test of Computers - Special Issue on 3D Integration; pp 520-531, Nov.-Dec. 2005.
2. C. Ababei; H. Mogal; K. Bazargan; Three-Dimensional Place and Route for FPGAs. In: Proceedings of the Design Automation Conference - Asia and South Pacific, ASP-DAC 2005. Volume: 2 18-21 Jan. 2005. Page(s); 773-778 Vol. 2.
3. C. Alpert; T. Chan; D. J. Huang.; I. Markov; K. Yan. Quadratic Placement Revisited. In: Proc. of the 34th Annual Conference on Design Automation, DAC 1997, New York, NY, USA. Anais... ACM Press, 1997, p.752-757.
4. K. Banerjee and S. Souri and P. Kapur and K. Saraswat. 3D-ICs: A Novel Chip Design for Improving Deep Submicrometer Interconnect Performance and Systems on-Chip Integration. Proceedings of IEEE, vol 89, issue 5, 2001.
5. R. Barret; M. Berry et al. Templates for the Solution of Linear Systems: Building Blocks for Iterative Methods. SIAM, 1994.
6. U. Brenner, A Pauli, J Vygen Almost Optimum Placement Legalization by Minimum Cost Flow and Dynamic Programming. -Proc. Int. Symp. on Physical Design, ISPD, 2004.
7. A. Caldwell, A. Kahng, and I. Markov. Can recursive bisection produce routable placements, Proc. ACM/IEEE Design Automation Conf., DAC, 2000, pp. 477-482.
8. W. R. Davis, J. Wilson, S. Mick, J. Xu, H. Hua, C. Mineo, A. M. Sule, M. Steer and P. D. Franzon; Demystifying 3D ICs: The Pros and Cons of Going Vertical. IEEE Design and Test of Computers -Special Issue on 3D Integration; pp 498-510, Nov.-Dec. 2005.
9. Y Deng; W. Maly. Interconnect Characteristics of 2.5-D System Integration Scheme. In: Proceedings of the International Symposium on Physical Design, ISPD 2001, New York, NY, USA. Anais... ACM Press, 2001. p.171-175.
10. B. Goplen; S. Sapatnekar; Efficient Thermal Placement of Standard Cells in 3D ICs usisng Forced Directed Approach. In:Proceedings of the Internation Conference on Computer Aided Design, ICCAD 2003, November, San Jose, California, USA, 2003.
11. R. Hentschke, S. Sawicki, M. Johann, R. Reis. An Algorithm for I/O Partitioning Targeting 3D Circuits and Its Impact on 3D-Vias, In IFIP Internation Conference on Very Large Scale Integration, VLSI-SOC 2006.
12. R. Hentschke; R. Reis. Improving Simulated Annealing Placement by Applying Random and Greedy Mixed Perturbations. Proceedings of the 16th Symposium on Integrated Circuits and Systems Design, SBCCI 2003, pp. 267-272.
13. ISPD 2004 - IBM Standard Cell Benchmarks with Pads. http://www.public. iastate.edu/~nataraj/ISPD04_Bench.html#Benchmark_Description. Access on Mar 2006.
14. G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar. Multilevel hypergraph partitioning: Application in VLSI domain. In Proceedings of 34th Annual Conference on. Design Automation, DAC 1997, pages 526-529, 1997.
15. D. Kershaw, The incomplete cholesky-conjugate gradient method for the iterative solution of systems of linear equations. Journal of Computational Physics, 26:43-65, 1978.
16. J. Lam and J. Delosme. Performance of a new annealing schedule. In: DAC '88: Proceedings. IEEE Computer Society Press, 1988, p.306-311.
17. S. Obenaus, T. Szymanski. Gravity: Fast Placement for 3D VLSI. ACM Transactions on Design Automation of Electronic Systems, New York, v.8, p.69-79, March 1999.
18. M. Sarrafzadeh and M. Wang. Nrg: global and detailed placement, Proc. IEEE/ACM International Conference on Computer-Aided Design, ICCAD, pp. 532-537, IEEE, 1997.
19. P. Villarrubia, "CPLACE: A Standard Cell Placement program" IBM Tech. Dis. Bull.,vol32 no. 10A, pp. 341-342, Mar. 1990.
20. N. Viswanathan; C.C.-N Chu. FastPlace: Efficient Analytical Placement Using Cell Shifting, Iterative Local Refinement,and a Hybrid Net Model. IEEE Transactions on CAD, Volume 24, Issue 5, pp 722-733, May 2005.
21. M. Wang, X. Yang, and M. Sarrafzadeh. Dragon2000: Standard-cell placement tool for large industry circuits. Proc. IEEE/ACM Int. Conf. Computer-Aided Design, ICCAD, 2000, pp. 260-263.