NoCs: A new contract between hardware and software

Proceedings - Euromicro Symposium on Digital System Design, DSD 2003

Volumn , Issue , 2003, Pages 10-16

  Jantsch, A ^a  

^a ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; COMPUTER SOFTWARE REUSABILITY; SEMANTICS; SYSTEMS ANALYSIS;

COMMUNICATION AND INTERACTION; DESIGN AND DEVELOPMENT; HARDWARE AND SOFTWARE; HARDWARE AND SOFTWARE COMPONENTS; NETWORK-ON-CHIP(NOC); PLATFORM IMPLEMENTATIONS; SEQUENTIAL ALGORITHM; TRADITIONAL COMPUTERS;

NETWORK-ON-CHIP;

ALGORITHMS; COMPUTATION; COMPUTER PROGRAMS;

EID: 34547244583     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2003.1231894     Document Type: Conference Paper

References (21)

1. A. Adriahantenaina, H. Charlery, A. Greiner, L. Mortiez, and C. A. Zeferino. SPIN: a scalable packet switched on-chip micronetwork. In Proceedings of the IEEE International Symposium on Circuits and Systems - Designer's Forum, pages 70-79, March 2003.
2. H. Chang, L. Cooke, M. Hunt, G. Martin, A. McNelly, and L. Todd. Surviving the SOC Revolution - A Guide to Platform-Based Design. Kluwer Academic Publishers, 1999.
3. W. J. Dally and B. Towles. Route packets, not wires: On-chip interconnection networks. In Proceedings of the 38th Design Automation Conference, June 2001.
4. K. Goossens, J. van Meerbergen, A. Peeters, and P. Wielage. Networks on silicon: Combining best-effort and guaranteed services. In Proceedings of the Design Automation and Test Conference, March 2002.
5. P. Guerrier and A. Greiner. A generic architecture for on-chip packet-switched interconnections. In Proceedings of Design, Automation and test in Europe, pages 250-256, 2000.
6. A. Hemani, A. Jantsch, S. Kumar, A. Postula, J. Öberg, M. Millberg, and D. Lindqvist. Network on chip: An architecture for billion transistor era. In Proceeding of the IEEE NorChip Conference, November 2000.
7. A. Jantsch and H. Tenhunen, editors. Networks on Chip. Kluwer Academic Publishers, February 2003.
8. A. Jantsch and H. Tenhunen. Will networks on chip close the productivity gap? In A. Jantsch and H. Tenhunen, editors, Networks on Chip, chapter 1, pages 3-18. Kluwer Academic Publishers, February 2003.
9. F. Karim, A. Nguyen, and S. Dey. An interconnect architecture for networking systems on chip. IEEE Micro, 22(5):36-45, September/October 2002.
10. K. Keutzer, S. Malik, R. Newton, J. Rabaey, and A. Sangiovanni-Vincentelli. System-level design: Orthogonalization of concerns and platform-based design. IEEE Trasnactions on Computer-Aided Design of Integrated Circuits and Systems, 19(12):1523-1543, Decmber 2000.
11. S. Kumar, A. Jantsch, J.-P. Soininen, M. Forsell, M. Millberg, J. Öberg, K. Tiensyrjä, and A. Hemani. A network on chip architecture and design methodology. In Proceedings of IEEE Computer Society Annual Symposium on VLSI, April 2002.
12. Z. Lu and A. Jantsch. Network-on-chip assembler language. Technical Report TRITA-IMIT-LECS R 03:02, version 1.0, Institute of Microelectronics and Information Technology, Royal Institute of Technology (KTH), Stockholm, Sweden, June 2003.
13. T. Makimoto. The rising wave of field programmability. In R. W. Hartenstein and H. Grnbacher, editors, Field-Programmable Logic and Applications, 10th International Workshop, FPL 2000, volume 1896 of Lecture Notes in Computer Science, Villach, Austria, August 2000.
14. E. Nilsson. Design and implementation of a hot-potato switch in a network on chip. Master's thesis, Department of Microelectronics and Information Technology, Royal Institute of Technology, IMIT/LECS 2002-11, Stockholm, Sweden, June 2002.
15. E. Nilsson, M. Millberg, J. Öberg, and A. Jantsch. Load distribution with the proximity congestion awareness in a network on chip. In Proceedings of the Design Automation and Test Europe (DATE), pages 1126-1127, March 2003.
16. E. Rijpkema, K. Goossens, A. Radulescu, J. Dielissen, J. van Meerbergen, P. Wielage, and E. Waterlander. Trade offs in the design of a router with both guaranteed and best effort services for networks on chip. In Proceedings of the Design Automation and Test Conference, pages 350-355, March 2003.
17. M. Sgroi, M. Sheets, A. Mihal, K. Keutzer, S. Malik, J. Rabaey, and A. Sangiovanni-Vincentelli. Addressing the system-on-a-chip interconnect woes through communication-based design. In Proceedings of the 38th Design Automation Conference, June 2001.
18. T. Valtonen, J. Isoaho, and H. Tenhunen. An atonomous error-tolerant cell for scalable network-on-chip architectures. In Proceedings of the 19th IEEE NorChip Conference, Kista, Sweden, November 2001.
19. T. Valtonen, T. Nurmi, J. Isoaho, and H. Tenhunen. Interconnection of autonomous error-tolerant cells. In Proceedings of the International Symposium on Circuits and Systems, Scottsdale, AZ, USA, 2002.
20. A. S. Vincentelli. Defining platform-based design. EEDesign of EETimes, February 2002.
21. D. Wingard. MicroNetwork-based integration of SOCs. In Proceedings of the 38th Design Automation Conference, June 2001.