Pareto optimal modeling for efficient PLL optimization

2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004

Volumn 2, Issue , 2004, Pages 195-198

  Tiwary, Saurabh Kumar ^a   Velu, Senthil ^a   Rutenbar, Rob A ^a   Mukherjee, Tamal ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

Analog circuits; Behavioral modeling; Circuit optimization; Pareto optimal design; Phase locked loop

Indexed keywords

AUTOMATION; COMPUTER SIMULATION; ELECTRIC CURRENTS; FREQUENCIES; NETWORKS (CIRCUITS); OPTIMIZATION; PARETO PRINCIPLE; TRANSISTORS;

ANALOG CIRCUITS; BEHAVIORAL MODELING; CICRUIT OPTIMIZATION; PARETO-OPTIMAL DESIGN;

PHASE LOCKED LOOPS;

EID: 6344237303     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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