Fast automatic sizing of a charge pump phase-locked loop based on behavioral models

BMAS 2005 - Proceedings of the 2005 IEEE International Behavioral Modeling and Simulation Workshop

Volumn 2005, Issue , 2005, Pages 100-105

  Zou, Jun ^a,b   Mueller, Daniel ^a   Graeb, Helmut ^a   Schlichtmann, Ulf ^a   Hennig, Eckhard ^b   Sommer, Ralf ^b  

^a TECHNICAL UNIVERSITY OF MUNICH   (Germany)

^b INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

Behavioral Modeling; Bottom Up; Hierarchical Sizing; Locking Time; Phase Margin; Top Down

Indexed keywords

COMPUTATION THEORY; COMPUTER SIMULATION; HIERARCHICAL SYSTEMS; PHASE CONTROL;

BEHAVIORAL MODELING; BOTTOM UP; HIERARCHICAL SIZING; LOCKING TIME; PHASE MARGIN; TOP DOWN;

PHASE LOCKED LOOPS;

EID: 33746798105     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/BMAS.2005.1518195     Document Type: Conference Paper

References (25)

1. H. Chang, A. Sangiovanni-Vincentelli, F. Balarin, etc, A Top-Down, Constraint-Driven Design Methodology for Analog Integrated Circuits, IEEE CICC, pp. 533-536, 1992.
2. G. G. E. Gielen and R. A. Rutenbar, Computer-Aided Design of Analog and Mixed-Signal Integrated Circuit, Proceeding of THE IEEE, VOL. 88 NO. 12 Dec. 2000.
3. I. Vassiliou, H. Chang, A. Demir, A. Sangiovanni-Vincentelli, A Video Driver System Designed Using a Top-Down Constraint-Driven Methodology, IEEE ICCAD, pp. 463-468, 1996.
4. B. A. A. Aanto, E. M. EL-Turky and R. H. Leonowich, Behavioral Modeling Phase-Locked Loops for Mixed-Mode Simulation, Analog Integrated Circuits and Signal Processing, No. 10, pp. 45-65, 1996.
5. P. Acco, M. P. Kennedy, C. Mira, B. Morley and B. Frigyik, Behavioral Modeling of Charge Pump Phase Locked Loops, IEEE ISCASS, pp. 375-378, 1999.
6. M. Hinz, I. Koenenkamp and E. H. Homeber, Behavioral Modeling and Simulation of Phase-Locked Loops for RF Front Ends, Proceeding of the 43rd IEEE MSCS, 2000.
7. K. Kundert, Predicting the phase noise and jitter of PLL-based frequency synthesizers, Available from http://www.designers-guide.org.
8. R. E. Best, Phase-Locked Loops Design, Simulation and Application, McGRAW-Hill, 2003.
9. B. Razavi, Design of Monolithic Phase-Locked Loops and Clock Recovery Circuits - a Tutorial. IEEE Press, 1996.
10. C. M. Chie and W.C. Lindsey, Phase-Locked Loops: Applications, Performance Measures and Summary of Analytical Results, IEEE Press, NY, 1986.
11. F. M. Gardner, Charge pump phase- locked loops, IEEE Trans. Communications, VOL. COM-28, No. 11, November 1980.
12. P. K. Hanumolu, M. Brownlee, K. Mayaram and U.K. Moon, Analysis of charge pump phase locked loops, IEEE Transactions of Circuit and System, VOL.51. No.9, Sept. 2004.
13. D. Müller, G. Stehr, H. Grab, U. Schlichtman, Deterministic Approaches to Analog Performance Space Exploration, IEEE DAC, 2005.
14. B. D. Smedt, G. E. Gielen, WATSON: Design Space Boundary Exploration and Model Generation for Analog and RF IC Design, IEEE Trans. CAD, 2003.
15. F. De Bernardinis, A. Sangiovanni-Vincentelli, A Methodology for System-Level Analog Design Space Exploration, IEEE DATE, 2004
16. H. Graeb, S. Zizala, J. Eckmueller, K. Antreich, The sizing rules method for analog integrated circuit design, IEEE/ACM ICCAD, pp. 343-349, 2001.
17. S. K. Tiwary, S.Velu, R. A. Rutenbar and T. Mukherjee, Pareto Optimal Modeling for Efficient PLL Optimization, Nanotech, Vol. 2 pp. 195 - 198, 2004.
18. Verliog-AMS Language Reference Manual: Analog & Mixed-Signal Extensions to Verilog-HDL, version 2.1. Available from www.verilog-ams.com.
19. W. Nye, D. Riley, and A. Sangiovanni-Vincentelli, An optimization-based system for the design of integrated circuits, IEEE ICCAD, 1988.
20. K. Antreich, J. Eckmueller, H. Graeb, M. Pronath, etc, WiCkeD: Analog circuit synthesis incorporating mismatch, IEEE CICC, pp. 511-514, May 2000.
21. F.Medeiro, F.V. Fernandez, Dominguez-Castro, A. Rodriguez-Vasquez, A statistical optimization-based approach for automated sizing of analog cells, IEEE/ACM ICCAD, 1994.
22. M. H. Perrott, Fast and Accurate Behavioral Simulation of Fractional-N Synthesizers and other PLL/DLL Circuit, IEEE DAC, pp. 498-503, June 2002.
23. www.muneda.com.
24. www.cadence.com.
25. www.mathworks.com.