Reliable low-power design in the presence of deep submicron noise

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 2000, Pages 295-302

  Shanbhag, Naresh ^a   Soumyanath, K ^a   Martin, Samuel ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; ENERGY EFFICIENCY; INTEGRATED CIRCUIT LAYOUT; SPURIOUS SIGNAL NOISE;

DEEP SUBMICRON NOISE (DSM); ERROR CONTROL CODING; SYSTEM ON CHIP (SOC);

CMOS INTEGRATED CIRCUITS;

EID: 0033652346     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/lpe.2000.155302     Document Type: Article

References (33)