Steady-State Analysis of Phase-Locked Loops using Binary Phase Detector

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 54, Issue 6, 2007, Pages 474-478

  Cheng, Shanfeng ^a   Tong, Haitao ^a   Silva Martinez, Jose ^a   Karsilayan, Aydin Ilker ^a  

^a Department of Electrical and Computer Engineering   (United States)

Author keywords

Bang bang phase detector (BPD); binary phase detector; clock and data recovery (CDR); phase locked loop (PLL)

Indexed keywords

CIRCUIT OSCILLATIONS; COMPUTER SIMULATION; ELECTRIC FILTERS; JITTER; WAVEFORM ANALYSIS;

BINARY PHASE DETECTOR; MOST STABLE OSCILLATION MODE (MSOM); STEADY STATE ANALYSIS; TRANSIENT WAVEFORM EQUATIONS;

PHASE LOCKED LOOPS;

EID: 34347406301     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2007.894429     Document Type: Article

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