Analysis of a half-rate bang-bang phase-locked-loop

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 49, Issue 7, 2002, Pages 505-509

  Ramezani, Mehrdad ^a   Andre, C ^a   Salama, T ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

Bang bang phase detector; Clock and data recovery; Jitter; Phase locked loop (PLL)

Indexed keywords

COMPUTER SIMULATION; ELECTRIC NETWORK ANALYSIS; TIME DOMAIN ANALYSIS; TIMING JITTER; VARIABLE FREQUENCY OSCILLATORS;

BANGBANG PHASE DETECTOR; BANGBANG VOLTAGE GENERATOR; CLOCK AND DATA RECOVERY;

PHASE LOCKED LOOPS;

EID: 0036663256     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSII.2002.805020     Document Type: Article

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