900MHz to 1.2GHz two-phase resonant clock network with programmable driver and loading

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2006, Pages 777-780

  Chueh, Juang Ying ^a   Sathe, Visvesh ^a   Papaefthymiou, Marios C ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

RESONANT CLOCK; RESONANT DISTRIBUTION NETWORKS;

AMPLITUDE MODULATION; CMOS INTEGRATED CIRCUITS; ENERGY EFFICIENCY; OSCILLATORS (ELECTRONIC);

ELECTRIC CLOCKS;

EID: 34347233532     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2006.320995     Document Type: Conference Paper

References (4)

1. S.C. Chan, P.J. Restle, K.L. Shepard, N.K James, and R.L. Franch, "A 4.6GHz resonant global clock distribution network," in Proceedings of IEEE international Solid-State Circuits Conference, Feb. 2004, vol. 1.
2. S.C. Chan, K.L. Shepard, and P.J. Restle, "1.1 to 1.6GHz distributed differential oscillator global clock network," in Proceedings of IEEE international Solid-State Circuits Conference, Feb. 2005, vol. 1.
3. A.J. Drake, K.J. Nowka, T.Y. Nguyen, J.L. Burns, and R.B. Brown, "Resonant clocking using distributed parasitic capacitance," IEEE Journal of Solid-State Circuits, vol. 39, no. 9, pp. 1520-1528, Sept. 2004.
4. W.C. Athas, J.G. Koller, and L."J." Svensson, "An energy-efficient CMOS line driver using adiabatic switching," USC/ISI technical report ACMOS-TR-2a, Nov. 3, 1993.