Dual-bit gate-sidewall storage FinFET NVM and new method of charge detection

IEEE Electron Device Letters

Volumn 28, Issue 6, 2007, Pages 502-505

  Padilla, Alvaro ^a   Shin, Kyoungsub ^a   King Liu, Tsu Jae ^a   Hyun, Jae Woong ^b   Yoo, Inkyeong ^b   Park, Yoondong ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b Samsung Advanced Institute of Technology (SAIT)   (South Korea)

Author keywords

Band to band electron injection; Field effect transistor (FET); FinFET; Gate induced drain leakage (GIDL); Nonvolatile memory (NVM)

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CONDUCTANCE; GATES (TRANSISTOR); LEAKAGE CURRENTS; SEMICONDUCTOR DEVICE MODELS;

BAND-TO-BAND ELECTRON INJECTION; GATE-INDUCED DRAIN LEAKAGE; NONVOLATILE MEMORY (NVM);

FIELD EFFECT TRANSISTORS;

EID: 34249806292     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2007.896786     Document Type: Article

References (16)

1. N. Lindert, L. Chang, Y.-K. Choi, E. H. Anderson, W.-C. Lee, T.-J. King, J. Bokor, and C. Hu, "Sub-60-nm quasi-planar FinFETs fabricated using a simplified process," IEEE Electron Device Lett., vol. 22, no. 10, pp. 487-489, Oct. 2001.
2. P. Xuan, M. She, B. Harteneck, A. Liddle, J. Bokor, and T.-J. King, "FinFET SONOS flash memory for embedded applications," in IEDM Tech. Dig., 2003, pp. 609-612.
3. M. Specht, R. Kommling, F. Hofmann, V. Klandzievski, L. Dreeskornfeld, W. Weber, J. Kretz, E. Landgraf, T. Schulz, J. Hartwich, W. Rosner, M. Stadele, R. J. Luyken, H. Reisinger, A. Graham, E. Hartmann, and L. Rish, "Novel dual bit tri-gate charge trapping memory devices," IEEE Electron Device Lett., vol. 25, no. 12, pp. 810-812, Dec. 2004.
4. F. Hofmann, M. Specht, U. Dorda, R. Kommling, L. Dreeskornfeld, J. Kretz, M. Stadele, W. Rosner, and L. Rish, "NVM based on FinFET device structures," Solid State Electron., vol. 49, no. 11, pp. 1799-1804, Nov. 2005.
5. C. W. Oh, S. D. Suk, Y. K. Lee, S. K. Sung, J.-D. Choe, S.-Y. Lee, D. U. Choi, K. H. Yeo, M. S. Kim, S.-M. Kim, M. Li, S. H. Kim, E.-J. Yoon, D.-W. Kim, D. Park, K. Kim, and B.-I. Ryu, "Damascene gate FinFET SONOS memory implemented on bulk silicon wafer," in IEDM Tech. Dig., 2004, pp. 893-896.
6. K. Kim, "Technology for sub-50 nm DRAM and NAND flash manufacturing," in IEDM Tech. Dig., 2005, pp. 323-326.
7. B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, and D. Finzi, "NROM: A novel localized trapping, 2-bit nonvolatile memory cell," IEEE Electron Device Lett., vol. 21, no. 11, pp. 543-545, Nov. 2000.
8. M. Fukuda, T. Nakanishi, and Y. Nara, "New nonvolatile memory with charge-trapping sidewall," IEEE Electron Device Lett., vol. 24, no. 7, pp. 490-492, Jul. 2003.
9. Taurus Process & Device User Manual, Synopsys, Inc., Mountain View, CA, 2003.
10. B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C.-Y. Yang, C. Tabery, C. Ho, Q. Xiang, T.-J. King, J. Bokor, C. Hu, M.-R. Lin, and D. Kyser, "FinFET scaling to 10 nm gate length," in IEDM Tech. Dig., 2002, p. 251.
11. K. Suzuki, T. Tanaka, Y. Tosaka, H. Horie, and Y. Arimoto, "Scaling theory for double-gate SOI MOSFET's," IEEE Trans. Electron Devices vol. 40, no. 12, pp. 2326-2329, Dec. 1993.
12. Y.-K. Choi, T.-J. King, and C. Hu, "Nanoscale CMOS spacer FinFET for the terabit era," IEEE Trans. Electron Devices, vol. 23, no. 1, pp. 25-27, Jan. 2002.
13. Y.-K. Choi, L. Chang, P. Ranade, J.-S. Lee, D. Ha, S. Balasubramanian, A. Agarwal, M. Ameen, T.-J. King, and J. Bokor, "FinFET process refinements for improved mobility and gate work function engineering," in IEDM Tech. Dig., 2002, pp. 259-262.
14. Y. Kamigaki, S. Minami, and H. Kato, "A new portrayal of electron and hole traps in amorphous silicon nitride," J. Appl. Phys., vol. 68, no. 5, pp. 2211-2215, 1990.
15. J. Chen, T. Y. Chan, I. C. Chen, P. K. Ko, and C. Hu, "Subbreakdown drain leakage current in MOSFET," IEEE Electron Device Lett., vol. EDL-8, no. 11, pp. 515-517, Nov. 1987.
16. S. Parke, J. Moon, P. Nee, J. Huang, C. Hu, and P. K. Ko, "Gate-induced drain leakage in LDD and fully-overlapped LDD MOSFETs," in VLSI Symp. Tech. Dig., 1991, pp. 49-50.