Accurate and computer efficient modelling of single event transients in CMOS circuits

IET Circuits, Devices and Systems

Volumn 1, Issue 2, 2007, Pages 137-142

  Wirth, G I ^a,b   Vieira, M G ^a   Lima Kastensmidt, F G ^b  

^a UNIVERSIDADE ESTADUAL DO RIO GRANDE DO SUL   (Brazil)

^b FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

[No Author keywords available]

Indexed keywords

INCIDENT PARTICLE; LOGIC GATE; SINGLE EVENT TRANSIENTS (SET); TRANSIENT PULSE AMPLITUDE;

CIRCUIT SIMULATION; COMPUTER AIDED DESIGN; ELECTRIC NETWORK TOPOLOGY; MOS DEVICES; SENSITIVITY ANALYSIS; TRANSIENTS;

CMOS INTEGRATED CIRCUITS;

EID: 34247895629     PISSN: 1751858X     EISSN: None     Source Type: Journal    
DOI: 10.1049/iet-cds:20050210     Document Type: Article

References (20)

1. Ziegler, J.F.: ' Terrestrial cosmic rays ', IBM J. Res. Dev., 1996, 40, (1), p. 19-40 0018-8646
2. Wirth, G.I., Vieira, M.G., and Kastensmidt, F.G.: ' Computer efficient modeling of SRAM cell sensitivity to SEU ', Proc. IEEE Latin American Test Workshop, Salvador, Brazil, 2005), p. 51-56
3. Shivakumar, P., Kistler, M., Keckler, S.W., Burger, D., and Alvisi, L.: ' Modelling the effect of technology trends on the soft error rate of combinational logic ', Int. Conf. on Dependable Systems and Networks 2002, 2001, Proceedings IEEE Computer Society, Piscataway, p. 389-398
4. Liden, P., Dahlgren, P., Johansson, R., and Karlsson, J.: ' On latching probability of particle induced transients in combinational networks ', 24th Inter. Symp. on Fault-Tolerant Computing (Digest of Papers, 1994), p. 340-349
5. Calvin, T., Vargas, F., Nicolaidis, M., and Velazco, R.: ' A low-cost, highly reliable SEU-tolerant SRAM: prototype and test results ', IEEE Trans. Nucl. Sci., 1995, 42, p. 1592-1598 0018-9499
6. Hazucha, P., Svensson, C., and Wender, S.: ' Cosmic-ray soft error characterization of a standard 0.6-m CMOS process ', IEEE J. Solid State Circuits, 2000, 35, p. 1422-1429
7. Palau, J.M., Calvet, M.C., Dodd, P.E., Sexton, F.W., and Roche, P.: ' Contribution of device simulation to SER understanding ', 41st, IEEE Int. Reliability Physics Symp., 2003, Dallas, TX, p. 71-75
8. Palau, J.M., Hubert, G., Coulie, K., Sagnes, B., and Calvet, M.C.: ' Device simulation study or the SEU sensitivity of SRAMs to ion tracks generated by nuclear reactions ', IEEE Trans. Nucl. Sci., 2001, 48, p. 225-231 10.1109/23.915368 0018-9499
9. Castellani-Coulié, K., Palau, J.M., Hubert, G., Calvet, M.C., Dodd, P.E., and Sexton, F.: ' Various SEU conditions in SRAM atudied by 3-D device Simulation ', IEEE Trans. Nucl. Sci., 2001, 48, p. 1931-1936 0018-9499
10. Yang, F.L., and Saleh, R.A.: ' Simulation and analysis of transient faults in digital circuits ', IEEE J. Solid State Circuits, 1992, 27, p. 258-264 10.1109/4.121546
11. Alexandrescu, D., Anghel, L., and Nicolaidis, M.: ' New methods for evaluating the impact of single event transients in VDSM ICs ', 7th, IEEE Int. Symp. on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002, Vancouver, BC, Canada, p. 99-107
12. Srinivasan, G.R.: ' Modelling the cosmic-ray-induced soft-error rate in integrated circuits: an overview ', IBM J. Res. Dev., 1996, 40, (1), p. 77-90 0018-8646
13. Dodd, P.E., and Massengill, L.W.: ' Basic mechanism and modeling of SEU in digital microelectronics ', IEEE Trans. Nucl. Sci., 2003, 50, p. 583-602 10.1109/TNS.2003.813129 0018-9499
14. Messenger, G.C.: ' Collection of charge on junction nodes from ion tracks ', IEEE Trans. Nucl. Sci., 1982, NS-29, p. 2024-2031 0018-9499
15. Eaton, P., Mavis, D., Avery, K., Sibley, M., Gadlage, M., and Turfingler, T.: ' Single event transient pulsewidth measurements using a variable temporal latch technique ', IEEE Trans. Nucl. Sci., 2004, 51, p. 3365-3368 10.1109/TNS.2004.840020 0018-9499
16. Hirata, A., Onodera, H., and Tamaru, K.: ' Proposal of a timing model for CMOS logic gates driving a CRC load ', Proc. 1998 IEEE/ACM Int. Conf. on Computer-Aided Design San Jose, CA, 1998, p. 537-544
17. Weste, N.H.E., and Eshraghian, K.: ' Principles of CMOS VLSI design: a systems perspective ', (Addison-Wesley Pub. Company, 1993)
18. Cha, H., and Patel, J.H.: ' A Logic-level model for alpha-particle hits in CMOS circuits ', Proc. IEEE Int. Conf. on Computer Design, 1993, p. 538-542
19. http://www.austriamicrosystems.com
20. http://www-device.eecs.berkeley.edu