Proposal of a timing model for CMOS logic gates driving a CRC π load

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1998, Pages 537-544

  Hirata, Akio ^a   Onodera, Hidetoshi ^a   Tamaru, Keikichi ^a  

^a KYOTO UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; EQUIVALENT CIRCUITS; MATHEMATICAL MODELS; OPTIMIZATION;

DEEP SUB-MICRON TECHNOLOGY; TIMING MODELS;

COMPUTER AIDED LOGIC DESIGN;

EID: 0032314949     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/288548.289083     Document Type: Conference Paper

References (13)