Scaling theory for FinFETs based on 3-D effects investigation

IEEE Transactions on Electron Devices

Volumn 54, Issue 5, 2007, Pages 1140-1147

  Yang, Wenwei ^a   Yu, Zhiping ^a   Tian, Lilin ^a  

^a TSINGHUA UNIVERSITY   (China)

Author keywords

Fin field effect transistor (FinFET); Scaling length; Subthreshold swing

Indexed keywords

COMPUTER SIMULATION; IONS; OPTIMIZATION; PERMITTIVITY; POISSON EQUATION;

FIN FIELD-EFFECT TRANSISTOR; SCALING LENGTH; SHORT-CHANNEL EFFECTS; SUBTHRESHOLD SWING;

FIELD EFFECT TRANSISTORS;

EID: 34247855788     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2007.893808     Document Type: Article

References (22)

1. [Online]. Available: http://www.itrs.net/Links/2006Update/ 2006UpdateFinal.htm
2. S. Thompson, P. Packan, and M. Bohr, "MOS scaling: Transistor challenges for the 21st century," Intel Technol. J., no. Q3, pp. 1-19, 1998.
3. C. S. Yin and P. C. H. Chan, "Investigation of the source/drain asymmetric effects due to gate misalignment in planar double-gate MOSFETs," IEEE Trans. Electron Devices, vol. 52, no. 1, pp. 85-90, Jan. 2005.
4. B. Doyle, B. Boyanov, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, R. Rios, and R. Chau, "Tri-gate fully-depleted CMOS transistors: Fabrication, design and layout," in VLSI Symp. Tech. Dig., 2003, pp. 133-134.
5. D. Hisamoto, W. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T. King, J. Bokor, and C. Hu, "FinFET - A self-aligned double-gate MOSFET scalable to 20 nm," IEEE Trans. Electron Devices vol. 47, no. 12, pp. 2320-2324, Dec. 2000.
6. J. M. Pimbley and J. D. Meindl, "MOSFET scaling limits determined by subthreshold conduction," IEEE Trans. Electron Devices, vol. 36, no. 9, pp. 1711-1721, Sep. 1989.
7. R. H. Yan, A. Ourmazd, and K. F. Lee, "Scaling the Si MOSFET: From bulk to SOI to bulk," IEEE Trans. Electron Devices, vol. 39, no. 6, pp. 1704-1710, Jul. 1992.
8. K. Suzuki, T. Tanaka, Y. Tosaka, H. Horie, and Y. Arimoto, "Scaling theory for double-gate SOI MOSFET's," IEEE Trans. Electron Devices vol. 40, no. 12, pp. 2326-2329, Dec. 1993.
9. Y. Tosaka, K. Suzuki, and T. Sugii, "Scaling-parameter-dependent model for subthreshold swing S in double-gate SOI MOSFET's," IEEE Trans. Electron Devices, vol. 15, no. 11, pp. 466-468, Nov. 1994.
10. T. K. Chiang, "A new scaling theory for fully depleted SOI double-gate MOSFET's: Including effective conducting path effect (ECPE)," Solid State Electron., vol. 49, no. 3, pp. 317-322, 2005.
11. H. T. Stephen, L. Chang, N. Lindert, Y. Choi, W. Lee, X. Huang, V. Subramanian, J. Bokor, T. King, and C. Hu, "FinFET - A quasiplanar double-gate MOSFET," in Proc. ISSC, 2001, pp. 118-119.
12. G. Pei, J. Kedzierski, P. Oldiges, M. Ieong, and E. C. C. Kan, "FinFET design considerations based on 3-D simulation and analytical modeling," IEEE Trans. Electron Devices, vol. 49, no. 8, pp. 1411-1419, Aug. 2002.
13. G. Katti, N. DasGupta, and A. DasGupta, "Threshold voltage model for mesa-isolated small geometry fully depleted SOI MOSFETs based on analytical solution of 3-D Poisson's equation," IEEE Trans. Electron Devices, vol. 51, no. 7, pp. 1169-1177, Jul. 2004.
14. D. S. Havaldar, G. Katti, N. DasGupta, and A. DasGupta, "Subthreshold current model of FinFETs Based on analytical solution of 3-D Poisson's equation," IEEE Trans. Electron Devices, vol. 53, no. 4, pp. 737-742, Apr. 2006.
15. X. Huang, W. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T. King, J. Bokor, and C. Hu, "Sub-50 nm P-channel FinFET," IEEE Trans. Electron Devices, vol. 48, no. 5, pp. 880-886, May 2001.
16. D. J. Frank, Y. Taur, and H. S. P. Wong, "Generalized scale length for two-dimensional effects in MOSFET's," IEEE Electron Device Lett., vol. 19, no. 10, pp. 385-387, Oct. 1998.
17. Q. Chen, B. Agrawal, and J. D. Meindl, "A compressive analytical sub-threshold swing (S) model for double-gate MOSFETs," IEEE Trans. Electron Devices, vol. 49, no. 6, pp. 1086-1090, Jun. 2002.
18. K. K. Young, "Short-channel effect in fully depleted SOI MOSFET's," IEEE Trans. Electron Devices, vol. 36, no. 2, pp. 399-402, Feb. 1989.
19. P. G. Harper, Introduction to Physical Mathematics. Cambridge, U.K.: Cambridge Univ. Press, 1995.
20. Taurus-Device User Guide, Synopsis Inc., Mountain View, CA, Sep. 2004. V-2004.
21. M. C. Lemme, T. Mollenhauer, W. Henschel, T. Wahlbrink, M. Baus, O. Winkler, R. Granzner, F. Schwierz, B. Spangenberg, and H. Kurz, "Subthreshold behavior of triple-gate MOSFETs on SOI material," Solid State Electron., vol. 48, no. 4, pp. 529-534, 2004.
22. H. S. P. Wong, D. J. Frank, and P. M. Solomon, "Device design consideration for double-gate, ground plane, single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation," in IEDM Tech. Dig. 1998, pp. 407-409.