Transistor level synthesis for static CMOS combinational circuits

Proceedings of the IEEE Great Lakes Symposium on VLSI

Volumn , Issue , 1999, Pages 172-175

  Liu, Chia Pin R ^a   Abraham, Jacob A ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASPECT RATIO; BOOLEAN FUNCTIONS; CMOS INTEGRATED CIRCUITS; COMBINATORIAL CIRCUITS; DATA STRUCTURES; DECISION THEORY; LOGIC GATES; OPTIMIZATION; TRANSISTORS;

BINARY DECISION DIAGRAM; TRANSISTOR LEVEL SYNTHESIS; TRANSISTOR MAPPED BINARY DECISION DIAGRAM;

INTEGRATED CIRCUIT LAYOUT;

EID: 0033365094     PISSN: 10661395     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)