Intrinsic mismatch between floating-gate nonvolatile memory cell and equivalent transistor

IEEE Electron Device Letters

Volumn 28, Issue 5, 2007, Pages 440-442

  Duane, Russell ^a   Rafhay, Quentin ^b   Beug, M Florian ^c   van Duuren, Michiel ^d  

^a UNIVERSITY COLLEGE CORK   (Ireland)

^b IMEP LAHC   (France)

^c QIMONDA DRESDEN GMBH AND CO OHG   (Germany)

^d NXP SEMICONDUCTORS   (Netherlands)

Author keywords

Nonvolatile memory devices; Plasma charging; Test structure

Indexed keywords

DATA STORAGE EQUIPMENT; NONVOLATILE STORAGE; PLASMAS; TRANSISTORS;

MEMORY CELL; PLASMA CHARGING; PLASMA-INDUCED DAMAGE;

ELECTRON DEVICES;

EID: 34247596525     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2007.895434     Document Type: Article

References (11)

1. M. Wong, D. K.-Y. Liu, and S. S.-W. Huang, "Analysis of the subthreshold slope and the linear transconductance techniques for the extraction of the capacitance coupling coefficients of floating gate devices," IEEE Electron Device Lett., vol. 13, no. 11, pp. 566-568, Nov. 1992.
2. R. Duane, A. Concannon, P. O'Sullivan, M. O'Shea, and A. Mathewson, "Extraction of coupling ratios for Fowler-Nordheim programming conditions," Solid State Electron., vol. 45, no. 2, pp. 235-242, Feb. 2001.
3. L. Larcher, P. Pavan, L. Albani, and T. Ghilardi, "Bias and W/L dependence of capacitive coupling coefficients in floating gate memory cells," IEEE Trans. Electron Devices, vol. 48, no. 9, pp. 2081-2089, Sep. 2001.
4. R. Duane, M. F. Beug, and A. Mathewson, "Novel capacitance coupling coefficient measurement methodology for floating gate non-volatile memory devices," IEEE Electron Device Lett., vol. 26, no. 7, pp. 507-509, Jul. 2005.
5. M. F. Beug, R. Duane, Q. Rafhay, and M. J. van Duuren, "Investigation of a new capacitance coupling coefficient measurement methodology for floating gate non-volatile memory cells," IEEE Trans. Electron Devices. submitted for publication.
6. F. Pio, P. Paruzzi, L. Baldi, and C. Riva, "Double-poly EEPROM cell for high density memories using positive and negative voltage programming," in Proc. ESSDERC, 1996, pp. 693-696.
7. H. Fang, S. Haddad, C. Chang, and J. Lien, "Plasma-induced in-line charging and damage in non-volatile memory devices," in IEDM Tech. Dig., 1994, pp. 467-470.
8. J. C. King and C. Hu, "Effect of low and high temperature anneal on process-induced damage of gate oxide," IEEE Electron Device Lett. vol. 15, no. 11, pp. 475-476, Nov. 1994.
9. K. P. Cheung, "Plasma charging damage to gate dielectric-past, present and future," in Proc. 9th Int. IPFA, 2002, pp. 237-241.
10. B. P. Linder and N. W. Cheung, "Calculating plasma damage as a function of gate oxide thickness," in Proc. 3rd Int. Symp. Plasma Process-Induced Damage, 1998, pp. 42-45.
11. Y.-B. Park and D. K. Schroder, "Degradation of thin tunnel gate oxide under constant Fowler-Nordheim current stress for a flash EEPROM," IEEE Trans. Electron Devices, vol. 45, no. 6, pp. 1361-1368, Jun. 1998.