Low-power fanout optimization using multiple threshold voltage inverters

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2005, Pages 95-98

  Amelifard, Behnam ^a   Fallah, Farzan ^b   Pedram, Massoud ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

^b FUJITSU LABORATORIES OF AMERICA   (United States)

Author keywords

Buffer chain; Fanout optimization; Fanout tree; Low power design

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; ENERGY DISSIPATION; OPTIMIZATION; THRESHOLD VOLTAGE;

BUFFER CHAIN; FANOUT OPTIMIZATION; FANOUT TREE; LOW-POWER DESIGN;

ELECTRIC INVERTERS;

EID: 28444433114     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/lpe.2005.195493     Document Type: Conference Paper

References (10)

1. Berman, C. L. , Carter, J. L., and Day, K. F. The fanout problem: from theory to practice. In Advanced Research in VLSI: Proc. of the 1989 Decennial Caltech Conf, MIT Press, 1989, 69-99.
2. Kodandapani, K., Grodstein, J., Domic, A. and Touati, H. A simple algorithm for fanout optimization using high-performance buffer libraries. In Proc. of ICCAD, 1993, 466-471.
3. th DAC., 1998, 352-355
4. Rezvani, P. and Pedram, M. A fanout optimization algorithm based on the effort delay model. IEEE Trans. on Computer-Aided Design, 22, (Dec. 2003), 1671-1678.
5. Sakurai, T. and Newton, A.R. A simple MOSFET model for circuit analysis. IEEE Trans. Electron Device, 38, (Apr. 1991), 887-894.
6. De, V., et al. Techniques for leakage power reduction in Chandrakasan, A., et al., Design of High-Performance Microprocessor Circuits. IEEE press, NJ, 2001, 46-62.
7. Vaidya, P. M. A new algorithm for minimizing convex functions over convex sets. In Proc. IEEE Foundations Comput. Sci., 1989, 332-337.
8. Sundararajan, V. and Parhi, K. Low power synthesis of dual threshold voltage CMOS VLSI circuits. In Proc. ISLPED, 1999.
9. Semiconductor Industry Association, International Technology Roadmap for Semiconductors, 2003 edition, http://public.itrs.net/.
10. Sirvastava, A. Simultaneous Vt selection and assignment for leakage optimization, in Proc. ISLPED, 2003.