Hierarchical buffered routing tree generation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 21, Issue 5, 2002, Pages 554-567

  Salek, Amir H ^a,b   Lou, Jinan ^a,c   Pedram, Massoud ^a,d  

^a IEEE   (United States)

^b PMC Sierra Inc   (United States)

^c SYNOPSYS INC   (United States)

^d University of Southern California   (United States)

Author keywords

Buffer insertion; Dynamic programming; Fanout optimization; Integrated circuits; Local order perturbation; Local search; Rectilinear Steiner tree

Indexed keywords

BUFFER INSERTION; FANOUT OPTIMIZATION; LOCAL ORDER PERTURBATION; POLYNOMIAL TIME ALGORITHM; RECTILINEAR STEINER TREE;

ALGORITHMS; COMPUTATIONAL COMPLEXITY; DYNAMIC PROGRAMMING; PERTURBATION TECHNIQUES; POLYNOMIALS; THEOREM PROVING; VLSI CIRCUITS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036576021     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.998627     Document Type: Article

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