Minimization of chip size and power consumption of high-speed VLSI buffers

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 1997, Pages 186-191

  Zhou, D ^a   Liu, X Y ^a   Wang, X L ^a  

^a UNIVERSITY OF NORTH CAROLINA AT CHARLOTTE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; VLSI CIRCUITS;

CHIP AREA; CIRCUIT DELAY; POWER CONSUMPTION; POWER DISSIPATION;

BUFFER CIRCUITS;

EID: 0030676715     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/267665.267711     Document Type: Conference Paper

References (18)