Chip-level performance maximization using ASIS (application-specific interconnect structure) wiring design concept for 45 nm CMOS generation

IEICE Transactions on Electronics

Volumn E90-C, Issue 4, 2007, Pages 848-855

  Oda, Noriaki ^a,c   Imura, Hironori ^a   Kawahara, Naoyoshi ^a   Tagami, Masayoshi ^a   Kunishima, Hiroyuki ^a   Sone, Shuji ^a   Ohnishi, Sadayuki ^a   Yamada, Kenta ^a   Kakuhara, Yumi ^a   Sekine, Makoto ^a   Hayashi, Yoshihiro ^b   Ueno, Kazuyoshi ^a,d  

^a RENESAS TECHNOLOGY CORP   (Japan)

^b NEC CORPORATION   (Japan)

^c SEMICONDUCTOR LEADING EDGE TECHNOLOGIES INC   (Japan)

^d SHIBAURA INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

Application; CMOS; Copper; Design; Interconnect; Low k

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CONDUCTIVITY; ELECTRIC WIRING; OPTIMIZATION; RELIABILITY;

APPLICATION-SPECIFIC INTERCONNECT STRUCTURE (ASIS); LOW-POWER APPLICATION;

INTERCONNECTION NETWORKS;

EID: 34247145524     PISSN: 09168524     EISSN: 17451353     Source Type: Journal    
DOI: 10.1093/ietele/e90-c.4.848     Document Type: Article

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