Technique to reduce the resolution requirement of digitally controlled oscillators for digital PLLs

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 54, Issue 3, 2007, Pages 237-241

  Hsieh, Ping Hsuan ^a   Yang, Chih Kong Ken ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Digital quantization; frequency resolution requirement; phase locked loops (PLLs); systematic jitter

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL CIRCUITS; JITTER; OSCILLATORS (ELECTRONIC);

DIGITAL QUANTIZATION; DIGITALLY CONTROLLED OSCILLATORS; FREQUENCY-RESOLUTION REQUIREMENT; SYSTEMATIC JITTER;

PHASE LOCKED LOOPS;

EID: 34147141811     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2006.889458     Document Type: Article

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