Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors

Proceedings -Design, Automation and Test in Europe, DATE

Volumn 1, Issue , 2006, Pages

  Raghavan, Praveen ^a,b   Lambrechts, Andy ^a,b   Jayapala, Murali ^a   Catthoor, Francky ^a,b   Verkest, Diederik ^a,b,c  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

^c VRIJE UNIVERSITEIT BRUSSEL   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; MULTIMEDIA SYSTEMS; MULTITASKING; SCALABILITY; VERY LONG INSTRUCTION WORD ARCHITECTURE;

DATA MEMORY; DISTRIBUTED INSTRUCTION MEMORY ORGANIZATION; UNI-PROCESSOR SYSTEM;

DISTRIBUTED COMPUTER SYSTEMS;

EID: 34047188078     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2006.243733     Document Type: Conference Paper

References (21)

1. 77 DSP Benchmark Suite. http://focus.ti.com/docs/toolsw/folders/ print/sprc092.html.
2. Trimaran: An Infrastructure for Research in Inststruction-Level Parallelism, http://www.trimaran.org, 1999.
3. R. Banakar et al. Scratchpad memory: A design alternative for cache on-chip memory in embedded systems. In Proc of CODES, May 2002.
4. L. Benini et al. A power modeling and estimation framework for vliw-based embedded system. ST Journal of System Research, 3(1): 110-118, April 2002. (Also presented in PATMOS 2001).
5. T. M. Conte et al. Instruction fetch mechanisms for VLIW architectures with compressed encodings. In Proc of MICRO, December 1996.
6. S. Cotterell et al. Synthesis of customized loop caches for core-based embedded systems. In Proc of ICCAD, November 2002.
7. W. Dally. Low power architectures. In ISSCC, Panel Talk on " When Processors Hit the Power Wall", February 2005.
8. H. De Man. Ambient intelligence: Giga-scale dreams and nano-scale realities. In Proc of ISSCC, Keynote Speech, February 2005.
9. A. El-Moursy et al. Partitioning multi-threaded processors with a large number of threads. In Proc of ISPASS, March 2005.
10. E.Ozer et al. Weld: A multithreading technique towards latency-tolerant vliw processors. In Proc of HiPC, 2001.
11. J. I. Gómez et al. Optimizing the memory bandwidth with loop morphing. In Proc of ASAP, pages 213-223, 2004.
12. A. Halambi et al. An efficient compiler technique for code size reduction using reduced bit-width ISAs. In Proc of DAC, March 2002.
13. M. Jayapala et al. Clustered loop buffer organization for low energy VLIW embedded processors. IEEE Trans on Computers, 54(6):672-683, June 2005.
14. M. Kandemir et al. Compiler-directed scratch pad memory optimization for embedded multiprocessors. In IEEE Trans on VLSI, pages 281-287, March 2004.
15. S. Kaxiras et al. Comparing power consumption of an smt and a cmp dsp for mobile phone workloads. In CASES, pages 211-220, November 2001.
16. A. Lambrechts et al. Power breakdown analysis for a heterogeneous NoC platform running a video application. In Proc of ASAP, pages 179-184, July 2005.
17. P. Op De Beeck et al. CRISP: A template for reconfigurable instruction set processors. In Proc of FPL, August 2001.
18. F. Quillere et al. Generation of efficient nested loops from polyhedra. In Intl. Journal on Parallel Programming, 2000.
19. J. W. Sias et al. Enhancing loop buffering of media and telecommunications applications using low-overhead predication. In Proc of MICRO, December 2001.
20. S. Steinke et al. Assigning program and data objects to scratchpad for energy reduction. In Proc of DATE, March 2002.
21. D. M. Tullsen et al. Simultaneous multithreading: Maximizing on-chip parallelism. In Proc of ISCA, pages 392-403, June 1995.