Optimizing the memory bandwidth with loop morphing

Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

Volumn , Issue , 2004, Pages 213-223

  Gomez, J I ^a   Marchai, P ^b   Verdoorlaege, S ^b   Pinuel, L ^a   Catthoor, F ^b  

^a UNIVERSIDAD COMPLUTENSE DE MADRID   (Spain)

^b UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

LOOP SPLITTING; MORPHING; SINGLE-PORT MEMORIES; SYSTEM'S PERFORMANCE;

DATA STRUCTURES; EMBEDDED SYSTEMS; ITERATIVE METHODS; OPTIMIZATION; SCHEDULING; STATIC RANDOM ACCESS STORAGE;

BANDWIDTH;

EID: 11244312192     PISSN: 10636862     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (20)

1. L. Benini and G. De Micheli. System-level power optimization: techniques and tools. TODAES, 5(2):115-192, 2000.
2. F. Bodin, et al. A quantitative algorithm for data locality optimization. In Proc. Int. Wkshp. on Code Generation, 1991.
3. K. Danckaert et al. A preprocessing step for global loop transformations for data transfer and storage optimization. CASES 2002.
4. D. Gannon et al. Strategies for cache and local memory management by global progra, optimizations. J. of Parallel and Distributed Systems, 25:587-617, 1988.
5. P. Grun et al. Memory Aware Compilation through Timing Extraction. In Proc. 37th Doc 2001.
6. Ken Kennedy and Kathryn S. McKinley. Maximizing loop parallelism and improving data locality via loop fusion and distribution. In 1993 Workshop on Languages and Compilers for Parallel Computing Portland, Ore., 1993. Berlin: Springer Verlag.
7. K.McKinley et al. Improving data locality with loop transformations. ACM Transactions on Programming Languages and Systems, 18(4):424-453, July 1996.
8. D. Kuck. Parallel Processing of ordinary programs. Advances in Computers, 15(4):119-179, 1976.
9. L. Lamport. The parallel execution of do-loops. Communications of ACM, 17(2):83-93, Feb. 1974.
10. A. W. Lim and M. S. Lam. Maximizing parallelism and minimizing synchronization with affine transforms. In Proceedings of the Twenty-fourth Annual ACM Symposium on the Principles of Programming Languages, Paris, France, 1997.
11. M.Wolf. Improving locality and parallelism in nested loops. Technical report, Technical report CSL-TR-92-538, Stanford Univ., CA, USA, Sep. 1992.
12. P. Panda et al. Exploiting Off-Chip Memory Access Modes in High-Level Synthesis. In Proc. Iccad, pages 333-340, Oct. 1997.
13. A. Porterfield. Software methods for improvement of cache performance on supercomputer applications. PhD thesis, Rice University, 1989.
14. P.Panda et al. Data and Memory Optimizations for Embedded Systems. ACM Trans. on Design Automation for Embedded Systems (TODAES), 6(2):142-206, Apr. 2001.
15. Y. Qian et al. Loop Fusion for Clustered VLIW Architectures. In Proc. Joint Conference on Languages, Compilers and Tools for Embedded Systems and Software and Compilers for Embedded Systems, pages 19-21, June 2002.
16. B. Rau. Iterative Modulo Scheduling. Technical report, HP Labs, 1995.
17. M. Saghir et al. Exploiting Dual Data Banks in Digital Signal Processors. In ASPLOS, Jun. 1996.
18. S. Verdoolaege et al. Multi-dimensional incremental loop fusion for data locality. In Proceedings 2003 Application-specific Systems, Architectures and Processors, pages 17-27, 2003.
19. W. Verhaegh et al. A Two-stage Solution Approach for Multidimensional Periodic Scheduling. IEEE Trans. Computer Aided Design of Integrated Circuits and Systems, 10(10):1185-1199, Oct. 2001.
20. S. Wuytack et al. Minimizing the required memory bandwidth in VLSI system realizations. IEEE Trans. VLSI Systems, 7(4):433-441, Dec. 1999.