메뉴 건너뛰기




Volumn 1, Issue , 2006, Pages

On-chip bus thermal analysis and optimization

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; OPTIMIZATION; PERMITTIVITY; THERMOANALYSIS; VLSI CIRCUITS;

EID: 34047138475     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (17)

References (18)
  • 8
    • 34047138094 scopus 로고    scopus 로고
    • http://www.simplescalar.com/.
  • 9
    • 4043167721 scopus 로고    scopus 로고
    • Low-Power Instruction Bus Encoding for Embedded Processors
    • August
    • P. Petrov and A.Orailoglu, "Low-Power Instruction Bus Encoding for Embedded Processors," IEEE Trans. on VLSI, pp. 812-826, August 2004.
    • (2004) IEEE Trans. on VLSI , pp. 812-826
    • Petrov, P.1    Orailoglu, A.2
  • 10
    • 0030644909 scopus 로고    scopus 로고
    • Asymptotic Zero-Transition Activity Encoding for Address Buses in Low-Power Microprocessor-Based Systems
    • March
    • L. Benini, G. De Micheli, E. Macii, D. Sciuto and C. Silvano, "Asymptotic Zero-Transition Activity Encoding for Address Buses in Low-Power Microprocessor-Based Systems," IEEE 7th Great Lakes Symposium on VLSI, pp. 77-82, March 1997.
    • (1997) IEEE 7th Great Lakes Symposium on VLSI , pp. 77-82
    • Benini, L.1    De Micheli, G.2    Macii, E.3    Sciuto, D.4    Silvano, C.5
  • 12
    • 34047098081 scopus 로고    scopus 로고
    • Irredundant Address Bus Encoding Techniques based on Adaptive Codebooks for Low Power
    • Aug
    • S. Komatsu and M. Fujita, "Irredundant Address Bus Encoding Techniques based on Adaptive Codebooks for Low Power," International Symposium on Low Power Design, pp. 9-14, Aug 2001.
    • (2001) International Symposium on Low Power Design , pp. 9-14
    • Komatsu, S.1    Fujita, M.2
  • 16
    • 34047144099 scopus 로고    scopus 로고
    • http://www-device.eecs.berkeley.edu/~ptm.
  • 17
    • 0034452632 scopus 로고    scopus 로고
    • Full Chip Thermal Analysis of Planar (2-D) and Vertically Integrated (3-D) High Performance ICs
    • S. Im and K. Banerjee, "Full Chip Thermal Analysis of Planar (2-D) and Vertically Integrated (3-D) High Performance ICs," In Proceedings of the IEDM, pp. 727-730, 2000.
    • (2000) Proceedings of the IEDM , pp. 727-730
    • Im, S.1    Banerjee, K.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.