On the evaluation of transactor-based verification for reusing TLM assertions and testbenches at RTL

Proceedings -Design, Automation and Test in Europe, DATE

Volumn 1, Issue , 2006, Pages

  Bombieri, Nicola ^a   Fummi, Franco ^a   Pravadelli, Graziano ^a  

^a UNIVERSITY OF VERONA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SIMULATION; ERROR ANALYSIS; VERIFICATION;

ASSERTION COVERAGE; SYSTEM LEVEL DESIGN; TRANSACTION LEVEL MODELING (TLM); TRANSACTOR BASED VERIFICATION (TBV);

SYSTEMS ANALYSIS;

EID: 34047111321     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2006.243898     Document Type: Conference Paper

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