Identification of Design Errors through Functional Testing

IEEE Transactions on Reliability

Volumn 52, Issue 4, 2003, Pages 400-412

  Ferrandi, Fabrizio ^a   Fummi, Franco ^b   Pravadelli, Graziano ^b   Sciuto, Donatella ^a  

^a POLITECNICO DI MILANO   (Italy)

^b UNIVERSITY OF VERONA   (Italy)

Author keywords

ATPG; Implementation verification; Symbolic techniques; Test synthesis

Indexed keywords

ATPG; IMPLEMENTATION; SYMBOLIC TECHNIQUES; TEST SYNTHESIS; VERIFICATION;

COMPUTER AIDED DESIGN; COMPUTER SIMULATION; ERROR DETECTION; SPECIFICATIONS;

COMPUTER HARDWARE DESCRIPTION LANGUAGES;

EID: 0742272649     PISSN: 00189529     EISSN: None     Source Type: Journal    
DOI: 10.1109/TR.2003.821926     Document Type: Article

References (48)

1. Formality Reference User's Manual: Synopsys Inc., 1998-2002.
2. "Formal Verification of SoC Designs by Using Unparalleled Capacity and Debug Capability of FormaPro Mentor Graphics Technical Paper,", 1997-2002.
3. K. L. McMillan, Symbolic Model Checking. Norwell Massachussets: Kluwer Academic Publishers, 1993
4. I. Beer, S. Ben-David, C. Eisner, and A. Lavander, "Rulebase, an industry-oriented formal verification tool," in ACM/IEEE Design Automation Conf., 1996, pp. 655-660.
5. Formal Check User's Manual: Cadence, 1999-2002.
6. Y. Abarbanel, I. Beer, L. Gluhovsky, S. Keidar, and Y. Wolfsthal, "FoCs - Automatic generation of simulation checkers from formal specifications," Computer Aided Verification, pp. 538-542, 2000.
7. H. Foster, "Applied boolean equivalence verification and RTL static sign-off," IEEE Design and Test of Computers, vol. 18, no. 4, pp. 6-15, 2001.
8. P. Azzoni, A. Fedeli, F. Fummi, G. Pravadelli, U. Rossi, and F. Toto, "An error simulation based approach to measure error coverage of formal properties," in ACM Great Lake Symp. VLSI, 2002.
9. G. J. Myers, The An of Software Testing. New York: Wiley - Interscience, 1979.
10. J. P. Bergmann and M. A. Horowitz, "Improving coverage analysis and test generation for large designs," in IEEE Int. Conf. Computer Aided Design, 1999, pp. 580-583.
11. J. Yuan, K. Shultz, C. Pixley, H. Miller, and A. Aziz, "Modeling design constraints and biasing in simulation using BDDS," in IEEE Int. Conf. Computer Aided Design, 1999, pp. 584-587.
12. D. L. Dill and S. Tasiran, "Embedded tutorial: Formal verification meets simulation," in IEEE Int. Conf. Computer Aided Design, 1999, pp. 221-222.
13. R. Vemuri and R. Kalyanaraman, "Generation of design verification tests from behavioral VHDL programs using path enumeration and constraint programming," IEEE Trans. VLSI Systems, vol. 3, no. 2, pp. 201-214, June 1995.
14. F. Fallah, P. Ashar, and S. Devadas, "Simulation vector generation from hdl descriptions for observability-enhanced statement coverage," in ACM/IEEE Design Automation Conf., 1999, pp. 666-671.
15. F. Fallah, S. Devadas, and K. Keutzer, "Functional vector generation for HDL models using linear programming and 3-satisfaiability," in Proc. ACM/IEEE Design Automation Conf., 1998, pp. 528-533.
16. D. Brahme and J. A. Abraham, "Functional testing of microprocessors," IEEE Trans. Comput., vol. C-33, pp. 475-485, 1985.
17. J. Lee and J. H. Patel, "Architectural level test generation for microprocessors," IEEE Trans. CAD/ICAS, vol. 13, no. 10, pp. 1288-1300, Oct. 1994.
18. K. T. Cheng and A. S. Krishnakumar, "Automatic generation of functional vectors using the extended finite state machine model," ACM Trans. Design Automation of Electronic Systems, vol. 1, no. 1, pp. 57-59, Jan. 1996.
19. U. h. Levendel and P. R. Menon, "Test generation algorithms for computer hardware description languages," IEEE Trans. Comput., vol. C-31, pp. 557-588, July 1982.
20. S. Ghosh and T. J. Chakraborty, "On behavior fault modeling for digital designs," J. Electronic Testing: Theory and Applications, vol. 2, pp. 135-151, 1991.
21. S. R. Rao, B. Y. Pan, and J. R. Armstrong, "Hierarchical test generation for VHDL behavioral models," in IEEE European Conf. Design Automation, 1993, pp. 175-182.
22. F. Fallah, S. Devadas, and K. Keutzer, "OCCOM: Efficient computation of observability-based code coverage metrics for functional verification," in ACM/IEEE Design Automation Conference, 1998, pp. 152-157.
23. D. Corvino, I. Epicoco, F. Ferrandi, F. Fummi, and D. Sciuto, "Automatic VHDL restructuring for RTL synthesis optimization and testability improvement," in IEEE Int. Conf. Computer Design, 1998, pp. 587-596.
24. F. Ferrandi, F. Fummi, E. Macii, M. Poncino, and D. Sciuto, "HDD-based testability estimation of VHDL designs," in IEEE European VHDL Conf., 1996, pp. 444-449.
25. H. Cho, G. D. Hachtel, E. Macii, B. Plessier, and F. Somenzi, "Algorithms for approximate FSM traversal based on space state decomposition," in ACM/IEEE Design Automation Conf., 1993, pp. 25-30.
26. F. Ferrandi, F. Fummi, and D. Sciuto, "Implicit test generation for behavioral VHDL models," in IEEE Int. Test Conf., 1998, pp. 436-441.
27. _, "Test generation and testability alternatives exploration of critical algorithms for embedded applications," IEEE Trans. Comput., vol. C-51, pp. 200-215, 2002.
28. G. Buonanno, L. Ferrandi, F. Ferrandi, F. Fummi, and D. Sciuto, "How an evolving fault model improves the behavioral test generation, " in ACM Great Lakes Symp. VLSI, 1997, pp. 124-129.
29. G. De Micheli, Synthesis and Optimization of Digital Circuits: Mc-Graw-Hill Series in Electrical and Computer Engineering, 1994.
30. (1992) 1991 and 1992 High Level Synthesis Benchmarks. [Online]. Available: ftp://mcnc.mcnc.org/pub/benchmark/HLSynth91(92)
31. IEEE Standard VHDL Language Reference Manual, IEEE Sid 1076-1993, 1993.
32. C. D. Kloos and P. T. Breuer, "Formal semantics for VHDL," in Kluwer International Series in Engineering and Computer Science, 1995.
33. T. Filkorn, M. Payer, and P. Warketin, "Symbolic verification of high-level synthesis results from callas," in Int. Workshop on High-level Synthesis, 1992, pp. 344-353.
34. R. Herrmann and H. Pargmann, "Computing binary decision diagrams for VHDL data types," in IEEE European Conf. Design Automation, 1994, pp. 578-585.
35. S. Minato, "Generation of BDDs from hardware algorithm descriptions," in IEEE Int. Conf. Computer Aided Design, 1996.
36. LEDA VHDL*Verilog System User's Manual. VHDL Compiler Version 4.1, 1993.
37. K. A. Barlett, R. K. Brayton, G. F. Hachtel, R. M. Jacoby, R. Rudell, and Sangiovanni-Vincentelli, "Don't care set specification in combinational and synchronous logic circuits," IEEE Trans. CAD/ICAS, vol. 7, pp. 723-739, June 1988.
38. H. Cho, G. D. Hachtel, S. W. Jeong, B. Plessier, E. Schwarz, and F. Somenzi, "ATPG aspects of FSM verification," in IEEE Int. Conf. Computer Aided Design. 1990.
39. Visual Architect User's Manual: Cadence, 1998.
40. I. Pomeranz and S. M. Reddy, "On static compaction of test sequences for synchronous sequential circuits," in ACM/IEEE Design Automation Conf., 1996, pp. 215-220.
41. M. S. Abadir, J. Ferguson, and T. E. Kirkland, "Logic design verification via test generation," IEEE Trans. CAD/ICAS, vol. 7, no. 1, pp. 138-148, Jan. 1988.
42. S. Kang and S. A. Szygenda, "Modeling and simulation of design errors," in IEEE Int. Conf. Computer Design, 1992, pp. 443-446.
43. S. Devadas, A. Ghosh, and K. Keutzer, "An observability-based code coverage metric for functional simulation," in IEEE Int. Conf. Computer Aided Design, 1996, pp. 418-425.
44. A. Fedeli, F. Fummi, G. Pravadelli, U. Rossi, and F. Toto, "On the use of a fault model to validate the completeness of a set of properties," in IEEE Microprocessor Test and Vefirication Workshop, 2002.
45. R. Bryant, "Graph-based algorithms for boolean function manipulation," IEEE Trans. Comput., vol. C-35, pp. 79-85, Aug. 1986.
46. O. Coudert, C. Berthet, and J. C. Madre, "Verification of sequential machines using boolean functional vectors," in Workshop on Applied Formal Methods for Correct VLSI Design, 1989.
47. R. Rudell, "Dynamic variable ordering for ordered binary decision diagrams," in ACM/IEEE Int. Conf. Computer Aided Design, 1993, pp. 42-47.
48. G. Jervan, Z. Peng, O. Goloubeva, M. S. Reorda, and M. Violante, "High-level and hierarchical test generation," IEEE High Level Design Validation and Teste, pp. 169-174, 2002.