Combining system level modeling with assertion based verification

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn , Issue , 2005, Pages 310-315

  Dahan, Anat ^a   Geist, Daniel ^a   Gluhovsky, Leonid ^a   Pidan, Dmitry ^a   Shapir, Gil ^a   Wolfsthal, Yaron ^a   Benalycherif, Lyes ^b   Kamdem, Romain ^b   Lahbib, Younes ^b  

^a IBM HAIFA RESEARCH LAB   (Israel)

^b STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ASSERTION-BASED VERIFICATION; COMBINING SYSTEMS; CONCURRENT LANGUAGES; FUNCTIONAL VERIFICATION; SYSTEM-LEVEL MODELING AND SIMULATION; SYSTEM-ON-CHIP; TEMPORAL ASSERTION; TRANSLATION SCHEMES;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER SIMULATION;

COMPUTER SOFTWARE;

EID: 84886665153     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2005.32     Document Type: Conference Paper

References (12)

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