Verification of transaction-level SystemC models using RTL testbenches

Proceedings - 1st ACM and IEEE International Conference on Formal Methods and Models for Co-Design, MEMOCODE 2003

Volumn , Issue , 2003, Pages 199-203

  Jindal, R ^a   Jain, K ^a  

^a CRnD ST Microelectronics   (India)

Author keywords

Costs; Design engineering; Design methodology; Hardware; Microelectronics; Partitioning algorithms; Programming; Software algorithms; System testing; Yarn

Indexed keywords

ABSTRACTING; ALGORITHMS; COMPUTER HARDWARE; COMPUTER SOFTWARE; COST ENGINEERING; COSTS; DESIGN; FORMAL METHODS; HARDWARE; IMAGE CODING; INTEGRATED CIRCUIT DESIGN; MATHEMATICAL PROGRAMMING; MICROELECTRONICS; MICROPROCESSOR CHIPS; SOFTWARE ENGINEERING; SOFTWARE TESTING; SYSTEM-ON-CHIP; VERIFICATION; YARN;

DESIGN ENGINEERING; DESIGN METHODOLOGY; PARTITIONING ALGORITHMS; SOFTWARE ALGORITHMS; SYSTEM TESTING;

SOFTWARE DESIGN;

EID: 84943596560     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MEMCOD.2003.1210104     Document Type: Conference Paper

References (4)

1. A.Clouard, G.Mastrorocco, F.Carbognani, A.Perrin, F.Ghenassia. "Towards Bridging the Precision Gap between SoC Transactional and Cycle Accurate Levels", DATE 2002
2. A.Ferrari and A.Sangiovanni - Vincentelli, System Design. "Traditional Concepts and New Paradigms". Proceedings of the 1999 Int. Conf. On Comp. Des, Oct 1999, Austin
3. "Functional Specification for SystemC 2.0", Version 2.0-P, Oct 2001
4. Frank Vahid, Tony Givargis. "Embedded SystemC Design : A Unified Hardware/Software Introduction". John Wiley & Sons,Inc