The improvement for transaction level verification functional coverage

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 5850-5853

  Zhong hai, Wang ^a   Yi zheng, Ye ^a  

^a HARBIN INSTITUTE OF TECHNOLOGY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT DESCRIPTION; COVERAGE METRICS; DIRECTED METHODS; FAULT INSERTION; FUNCTIONAL COVERAGE; FUNCTIONAL VERIFICATION; HARDWARE DESIGN; HARDWARE DESIGN LANGUAGE; RANDOM TEST GENERATION; TRANSACTION LEVEL; TRANSACTION-LEVEL VERIFICATION;

HARDWARE;

COMPUTER SIMULATION LANGUAGES;

EID: 48849099221     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1465969     Document Type: Conference Paper

References (13)

1. F. Fallah, MIT, P. Ashar, CCRL and S. Devadas, Functional Vector Generation for Sequential HDL Models Under an Observability- Based Code Coverage Metric, IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2002, pp.919-923.
2. Qiushuang Zhang, and Ian G. Harris, A data flow fault coverage metric for validation of behavioral HDL descriptions, ICCAD'00. 2000, pp.369-373
3. Surrendra Dudani, and Jayant Nagda, High Level Functional Verification Closure, ICCD2002. 2002, pp.91-96
4. Rohit Jindal, and Kshitiz Jain, Verification of Transaction-Level SystemC models using RTL Testbenches, MEMOCODE 2003, pp.199-203
5. Fotis Andritsopoulos, C. Charopoulos, Gregory Doumenis, Fotis Karoubalis, Yannis Mitsos, et al, Verification of a Complex SoC: The PRO3 Case-Study, DATE 2003, pp.20224-20231
6. S. Pasricha, Transaction Level Modelling of SoC with SystemC 2.0. In Synopsys User Group Conference, 2002.
7. P. Paulin et al. StepNP: A System-Level Exploration Platform for Network Processors. In IEEE Trans. On Design and Test, Nov-Dec 2002.
8. Richard Goering, DAI introduces Test-Generation Tool, EE Times, November 17, 1998
9. Steve Forde, Steve Bishop, and Ramnath S. Velu, Streamling HDL Code Coverage Analysis, Integrated Systems Design, Desember, 1998
10. Lukai Cai, and Daniel Gajski, Transaction Level Modeling: An Overview, Proc. 1st IEEE Intl. Conf. on Hardware/Software Codesign & System Synthesis, 2003, pp. 19-24
11. S. Chonnad, and B. Needamangalam, A Layered Approach to Behavioral Modeling of Bus Protocols, ASIC2000, pp170-173
12. Y. Tohma, et. al., Structural approach to the estima- tions of the number of residual software fault based on hypergeometric distribution, IEEE Trans. Software Engineering, 1989, pp.345-355
13. Piwowarski P., Ohba M.; and Caruso J. Coverage Measurement Experience During Function Test, Proceedings of the 15th International Conference on Software, 1993, pp.287-301