Modeling and characterization of effects of dummy-date bias on LDMOSFETs

IEEE Transactions on Electron Devices

Volumn 54, Issue 3, 2007, Pages 580-588

  Marbell, Marvin N ^a   Cherepko, Sergey V ^b   Hwang, James C M ^a   Shibib, M Ayman ^c   Curtice, Walter R ^d  

^a LEHIGH UNIVERSITY   (United States)

^b ANALOG DEVICES INC   (United States)

^c INFINEON TECHNOLOGIES AG   (Germany)

^d WR Curtice Consulting   (United States)

Author keywords

Adaptive bias; Berkeley short channel IGFET model (BSIM); Dummy gate; Efficiency enhancement; Field plate; Laterally diffused MOS (LDMOS); Model; MOSFET; Radio frequency (RF) power

Indexed keywords

CAPACITANCE; CHARACTERIZATION; COMPUTER SIMULATION; DRAIN CURRENT; ELECTRIC RESISTANCE; GATES (TRANSISTOR); RADIO FREQUENCY AMPLIFIERS; SEMICONDUCTING SILICON;

BERKELEY SHORT-CHANNEL IGFET MODEL; DUMMY GATE; LATERALLY DIFFUSED MOSFET; RADIO-FREQUENCY POWER;

MOSFET DEVICES;

EID: 33947656935     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2006.890586     Document Type: Article

References (20)

1. M.-R. Lee and O.-K. Kwon, "High performance extended drain MOSFETs (EDMOSFETs) with metal field plate," in Proc. Int. Symp. Power Semicond. Devices, May 1999, pp. 249-252.
2. A. Wood, W. Brakensick, C. Dragon, and W. Burger, "120 Watt, 2 GHz, Si LDMOS RF power transistor for PCS base station applications," in Proc. IEEE MTT-S Int. Microw. Symp. Dig., Jun. 1998, pp. 707-710.
3. S. Xu, F. Baiocchi, H. Safar, J. Lott, A. Shibib, Z. Xie, T. Nigam, B. Jones, B. Thompson, J. Desko, and P. Gammel, "High power silicon RF LDMOSFET technology for 2.1 GHz power amplifier applications," in Proc. Int. Symp. Power Semicond. Devices, Apr. 2003, pp. 190-193.
4. S. Xu, C. Ren, Y. C. Liang, P.-D. Foo, and J. K. O. Sin, "Theoretical analysis and experimental characterization of the dummy-gated VDMOSFET," IEEE Trans. Electron Devices, vol. 48, no. 9, pp. 2168-2176, Sep. 2001.
5. A. Shibib, S. Xu, Z. Xie, P. Gammel, M. Mastrapasqua, and I. Kizilyalli, "Control of hot carrier degradation in LDMOS devices by a dummy gate field plate: Experimental demonstration," in Proc. Int. Symp. Power Semicond. Devices, May 2004, pp. 233-235.
6. ATLAS User's Manual, Silvaco Int., Santa Clara, CA, Sep. 2004.
7. Verilog-A Reference Manual, Cadence Des. Syst., Inc., San Jose, CA, Aug. 2005.
8. BSIM4.3.0 User's Manual, Univ. California, Berkeley, CA, 2003.
9. M. N. Marbell, J. C. M. Hwang, W. Dai, M. Frei, and M. A. Shibib, "A Verilog-based temperature-dependent BSIM4 model for RF power LDMOSFETs," in Proc. IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2005, pp. 1163-1166.
10. M. N. Marbell, S. V. Cherepko, A. Madjer, J. C. M. Hwang, M. Frei, and M. A. Shibib, "An improved large-signal model for harmonic-balance simulation of Si LD-MOSFETs," in Proc. 34th Eur. Microw. Conf., Oct. 2004, pp. 225-228.
11. E. C. Griffith, J. A. Power, S. C. Kelly, P. Elebert, S. Whiston, D. Bain, and M. O'Neill, "Characterization and modeling of LDMOS transistors on a 0.6 um CMOS technology," in Proc. Int. Conf. Microelectron. Test Struct., 2000, pp. 175-180.
12. Y. Yang, Y. Woo, J. Yi, and B. Kim, "A new empirical large-signal model of Si LDMOSFETs for high-power amplifier design," IEEE Trans. Microw. Theory Tech., vol. 49, no. 9, pp. 1626-1633, Sep. 2001.
13. W. R. Curtice, J. A. Pla, D. Bridges, T. Liang, and E. E. Shumate, "A new dynamic electro-thermal nonlinear model for silicon RF LDMOS FETs," in Proc. IEEE MTT-S Int. Microw. Symp. Dig., Jun. 1999, pp. 419-422.
14. M. Miller, T. Dinh, and E. Shumate, "A new empirical large signal model for silicon RF LDMOS FETs," in Proc. IEEE MTT-S Symp. Technol. Wireless Appl. Dig., Feb. 1997, pp. 19-22.
15. J. Jang, O. Tornblad, T. Arnborg, Q. Chen, K. Barnerjee, Z. Yu, and R. W. Dutton, "RF LDMOS characterization and its compact modeling," in Proc. IEEE MTT-S Int. Microw. Symp. Dig., May 2001, pp. 967-970.
16. P. Perugupalli, M. Trivedi, K. Shenai, and S. K. Leong, "Modeling and characterization of an 80-V silicon LDMOSFET for emerging RFIC applications," IEEE Trans. Electron Devices, vol. 45, no. 9, pp. 1468-1478, Jul. 1998.
17. O. Tornblad and C. Blair, "An electrothermal BSIM3 model for large-signal operation of RF power LDMOS devices," in Proc. IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2002, pp. 861-864.
18. I. Cortés, J. Roig, D. Flores, J. Urresti, S. Hidalgo, and J. Rebollo, "A numerical study of field plate configurations in RF SOI LDMOS transistors," Solid State Electron., vol. 50, no. 2, pp. 155-163, Feb. 2006.
19. J. Staudinger, B. Gilsdorf, D. Newman, G. Norris, G. Sadowniczak, R. Sherman, and T. Quach, "High efficiency CDMA RF power amplifier using dynamic envelope tracking technique," in Proc. IEEE MTT-S Int. Microw. Symp. Dig., Jun. 2000, pp. 873-876.
20. F. Wang, A. H. Yang, D. F. Kimball, L. E. Larson, and P. M. Asbeck, "Design of wide-bandwidth envelope-tracking power amplifiers for OFDM applications," IEEE Trans. Microw. Theory Tech., vol. 53, no. 4, pp. 1244-1255, Apr. 2005.