A numerical study of field plate configurations in RF SOI LDMOS transistors

Solid-State Electronics

Volumn 50, Issue 2, 2006, Pages 155-163

  Cortes I ^a   Roig, J ^b   Flores, D ^a   Urresti, J ^a   Hidalgo, S ^a   Rebollo, J ^a  

^a INSTITUTO DE MICROELECTRÓNICA DE BARCELONA   (Spain)

^b LAAS CNRS   (France)

Author keywords

Capacitance analysis; Field plate; RF LDMOS; Self heating; SOI technology; Transconductance

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; DEGRADATION; ELECTRIC RESISTANCE; HEATING; MOS DEVICES; TRANSCONDUCTANCE;

FIELD PLATE; RF-LDMOS; SELF-HEATING; SOI TECHNOLOGY;

SILICON ON INSULATOR TECHNOLOGY;

EID: 32344445436     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2005.11.003     Document Type: Article

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