Characterization and modeling of LDMOS transistors on a 0.6μm CMOS technology

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 2000, Pages 175-180

  Griffith, E C ^a   Power, J A ^a   Kelly, S C ^a   Elebert, P ^a   Whiston, S ^a   Bain, D ^a   O'Neill, M ^a  

^a ANALOG DEVICES   (Ireland)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC BREAKDOWN; ELECTRIC CURRENTS; ELECTRIC RESISTANCE; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS;

FEEDBACK CAPACITANCE; GATE OXIDE; HIGH VOLTAGE INTEGRATED CIRCUITS; INTERCONNECT METALLIZATION EFFECT; LATERAL DOUBLE DIFFUSED TRANSISTOR; POLYSILICON; SATURATION CURRENT;

MOSFET DEVICES;

EID: 0033718061     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)