Evaluation of the statistical delay quality model

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 1, Issue , 2005, Pages 305-310

  Sato, Yasuo ^a   Hamada, Shuji ^a   Maeda, Toshiyuki ^a   Takatori, Atsuo ^a   Kajihara, Seiji ^b  

^a KYUSHU INSTITUTE OF TECHNOLOGY   (Japan)

^b SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; PRODUCT DESIGN; QUALITY ASSURANCE;

BENCHMARK DATA; CHIP DEFECTS; CHIP QUALITY; DESIGN DELAYS; FABRICATION PROCESS; QUALITY MODELING; STATISTICAL DELAYS; TESTING COSTS;

BENCHMARKING;

EID: 84861443625     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1120725.1120856     Document Type: Conference Paper

References (14)

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