-
2
-
-
0003502725
-
-
Norwell, MA: Kluwer
-
F. Catthoor, K. Danckaert, C. Kulkarni, E. Brockemeyer, P. G. Kjeldsberg, T. Van Achteren, and T. Omnes, Storage Management for Embedded Programmable Processors. Norwell, MA: Kluwer, 2002.
-
(2002)
Storage Management for Embedded Programmable Processors
-
-
Catthoor, F.1
Danckaert, K.2
Kulkarni, C.3
Brockemeyer, E.4
Kjeldsberg, P.G.5
Van Achteren, T.6
Omnes, T.7
-
4
-
-
84979939129
-
Bit-width selection for data-path implementations
-
San Jose, CA
-
C. Carreras, J. A. Lopez, and O. Nieto-Taladriz, "Bit-width selection for data-path implementations," in Proc. 12th Int. Symp. Syst. Synth., San Jose, CA, 1999, pp. 114-119.
-
(1999)
Proc. 12th Int. Symp. Syst. Synth
, pp. 114-119
-
-
Carreras, C.1
Lopez, J.A.2
Nieto-Taladriz, O.3
-
5
-
-
13144273032
-
Quality-driven design by bit-width optimization for video applications
-
Kitakyushu, Japan
-
Y. Cao and H. Yasuura, "Quality-driven design by bit-width optimization for video applications," in Proc. Conf. Asia and South Pacific Des. Autom., Kitakyushu, Japan, 2003, pp. 532-537.
-
(2003)
Proc. Conf. Asia and South Pacific Des. Autom
, pp. 532-537
-
-
Cao, Y.1
Yasuura, H.2
-
6
-
-
0036050384
-
FPGA resource and timing estimation from Matlab execution traces
-
Estes Park, CO
-
P. Bjuréus, M. Millberg, and A. Jantsch, "FPGA resource and timing estimation from Matlab execution traces," in Proc. 10th Int. Symp. Hardware/Software Codes., Estes Park, CO, 2002, pp. 31-36.
-
(2002)
Proc. 10th Int. Symp. Hardware/Software Codes
, pp. 31-36
-
-
Bjuréus, P.1
Millberg, M.2
Jantsch, A.3
-
7
-
-
32544453450
-
IMEM: An object-oriented memory- and interface modelling approach for realime video systems
-
Marseille, France, CD-ROM
-
B. Thörnberg, H. Norell, and M. O'Nils, "IMEM: An object-oriented memory- and interface modelling approach for realime video systems," in Proc. Forum Specification and Des. Lang., Marseille, France, 2002. [CD-ROM].
-
(2002)
Proc. Forum Specification and Des. Lang
-
-
Thörnberg, B.1
Norell, H.2
O'Nils, M.3
-
8
-
-
33947602480
-
Conceptual interface and memory-modelling for real-time image processing systems
-
St. Thomas, VI
-
_, "Conceptual interface and memory-modelling for real-time image processing systems," in Proc. 5th IEEE Int. Workshop Multimedia Signal Process., St. Thomas, VI, 2002, pp. 138-141.
-
(2002)
Proc. 5th IEEE Int. Workshop Multimedia Signal Process
, pp. 138-141
-
-
Thörnberg, B.1
Norell, H.2
O'Nils, M.3
-
9
-
-
0034795611
-
SystemC - A modelling platform supporting multiple design abstractions
-
Montreal, QC, Canada
-
P. R. Panda, "SystemC - A modelling platform supporting multiple design abstractions," in Proc. 14th Int. Svmp. Syst. Synth., Montreal, QC, Canada, 2001, pp. 75-80.
-
(2001)
Proc. 14th Int. Svmp. Syst. Synth
, pp. 75-80
-
-
Panda, P.R.1
-
12
-
-
32544459769
-
Polyhedral space generation and memory estimation from interface and memory nodels of real-time video systems
-
B. Thörnberg, Q. Hu, M. Palkovic, M. O'Nils, and P. G Kjeldsberg, "Polyhedral space generation and memory estimation from interface and memory nodels of real-time video systems," J. Syst. Softw., vol. 79, no. 2, pp. 231-245, 2005.
-
(2005)
J. Syst. Softw
, vol.79
, Issue.2
, pp. 231-245
-
-
Thörnberg, B.1
Hu, Q.2
Palkovic, M.3
O'Nils, M.4
Kjeldsberg, P.G.5
-
13
-
-
2942564431
-
Storage requirement estimation for optimized design of data intensive applications
-
P. G. Kjeldsberg, F. Catthoor, and E. J. Aas, "Storage requirement estimation for optimized design of data intensive applications," ACM Trans. Des. Autom. Electron. Syst., vol. 1, no. 2, pp. 133-158, 2004.
-
(2004)
ACM Trans. Des. Autom. Electron. Syst
, vol.1
, Issue.2
, pp. 133-158
-
-
Kjeldsberg, P.G.1
Catthoor, F.2
Aas, E.J.3
-
14
-
-
0031674736
-
System-level data-flow transformation exploration and power-area trade-offs demonstrated on video codecs
-
F. Catthoor et al., "System-level data-flow transformation exploration and power-area trade-offs demonstrated on video codecs," J. VLSI Signal Process. Syst. Signal Image Video Technol., vol. 18, no. 1, pp. 39-50, 1998.
-
(1998)
J. VLSI Signal Process. Syst. Signal Image Video Technol
, vol.18
, Issue.1
, pp. 39-50
-
-
Catthoor, F.1
-
15
-
-
0020504458
-
Optimizing synchronous circuitry by retiming
-
Pasadena, CA
-
C. E. Leiserson, F. M. Rose, and J. B. Saxe, "Optimizing synchronous circuitry by retiming," in Proc. 3rd Caltech Conf. Very Large Scale Integr., Pasadena, CA, 1983, pp. 87-116.
-
(1983)
Proc. 3rd Caltech Conf. Very Large Scale Integr
, pp. 87-116
-
-
Leiserson, C.E.1
Rose, F.M.2
Saxe, J.B.3
-
16
-
-
0030286417
-
Achieving full parallelism using multidimensional retiming
-
Nov
-
N. Passos and E. Sha, "Achieving full parallelism using multidimensional retiming," IEEE Trans. Parallel Distrib. Syst., vol. 7, no. 11, pp. 1150-1163, Nov. 1996.
-
(1996)
IEEE Trans. Parallel Distrib. Syst
, vol.7
, Issue.11
, pp. 1150-1163
-
-
Passos, N.1
Sha, E.2
-
17
-
-
0029517120
-
Buffering of intermediate results in dataflow diagrams
-
Darmstadt, Germany
-
A. Woodruff and M. Stonebraker, "Buffering of intermediate results in dataflow diagrams," in Proc. 11th IEEE Int. Symp. Visual Lang., Darmstadt, Germany, 1995, pp. 187-194.
-
(1995)
Proc. 11th IEEE Int. Symp. Visual Lang
, pp. 187-194
-
-
Woodruff, A.1
Stonebraker, M.2
-
18
-
-
0030674745
-
Synthesis of parallel hardware implementations from synchronous dataflow graph specification
-
Pacific Grove, CA
-
M. C. Williamson and E. A. Lee, "Synthesis of parallel hardware implementations from synchronous dataflow graph specification," in Proc. Conf. Rec, 30th Asilomar Conf. Signals, Syst. and Comput., Pacific Grove, CA, 1996, pp. 1340-1343.
-
(1996)
Proc. Conf. Rec, 30th Asilomar Conf. Signals, Syst. and Comput
, pp. 1340-1343
-
-
Williamson, M.C.1
Lee, E.A.2
-
19
-
-
0032633135
-
Buffer memory requirements in DSP applications
-
M. Adé, R. Lawereins, and J. A. Peperstraete, "Buffer memory requirements in DSP applications," Comput. Syst. Sci. Eng., vol. 14, no. 3, pp. 155-165, 1999.
-
(1999)
Comput. Syst. Sci. Eng
, vol.14
, Issue.3
, pp. 155-165
-
-
Adé, M.1
Lawereins, R.2
Peperstraete, J.A.3
-
20
-
-
0031381304
-
Parameterized polyhedra and their vertices
-
V. Loechner and D. Wilde, "Parameterized polyhedra and their vertices," Int. J. Parallel Program., vol. 25, no. 6, pp. 525-549, 1997.
-
(1997)
Int. J. Parallel Program
, vol.25
, Issue.6
, pp. 525-549
-
-
Loechner, V.1
Wilde, D.2
-
21
-
-
0004005802
-
A library for doing polyhedral operations,
-
M.S. thesis, Oregon State Univ, Corvallis, OR, Also published in IRISA technical report PI Rennes, France
-
D. K. Wilde, "A library for doing polyhedral operations," M.S. thesis, Oregon State Univ., Corvallis, OR, 1993. Also published in IRISA technical report PI 785 Rennes, France 1993.
-
(1993)
, pp. 785
-
-
Wilde, D.K.1
-
22
-
-
0032068586
-
Automatic storage management for parallel programs
-
V. Lefebrev and P. Feautrier. "Automatic storage management for parallel programs," Parallel Comput., vol. 24, no. 3/4, pp. 649-671, 1998.
-
(1998)
Parallel Comput
, vol.24
, Issue.3-4
, pp. 649-671
-
-
Lefebrev, V.1
Feautrier, P.2
-
23
-
-
0024054628
-
Compiler optimizations for enhancing parallelism and their impact on architecture design
-
C. Polychronopoulos, "Compiler optimizations for enhancing parallelism and their impact on architecture design," IEEE Trans. Comput., vol. 37, no. 8, pp. 991-1004, 1998.
-
(1998)
IEEE Trans. Comput
, vol.37
, Issue.8
, pp. 991-1004
-
-
Polychronopoulos, C.1
-
24
-
-
0033075413
-
Improving cache locality by a combination of loop and data transformations
-
Feb
-
M. Kandemir, J. Ramanujam, and A. Choudhary, "Improving cache locality by a combination of loop and data transformations," IEEE Trans. Comput., vol. 48, no. 2, pp. 159-167, Feb. 1999.
-
(1999)
IEEE Trans. Comput
, vol.48
, Issue.2
, pp. 159-167
-
-
Kandemir, M.1
Ramanujam, J.2
Choudhary, A.3
-
25
-
-
0034592553
-
A preprocessing step for global loop transformations for data transfer optimization
-
San Jose, CA
-
K. Danckaert, F. Catthoor, and H. De Man, "A preprocessing step for global loop transformations for data transfer optimization," in Proc. Int. Conf. CASES, San Jose, CA, 2000, pp. 34-40.
-
(2000)
Proc. Int. Conf. CASES
, pp. 34-40
-
-
Danckaert, K.1
Catthoor, F.2
De Man, H.3
-
26
-
-
33947585129
-
A generalized architecture for hardware synthesis of spatio-temporal memory models for image processing systems
-
Chalkida, Greece
-
H. Norell and M. O'Nils, "A generalized architecture for hardware synthesis of spatio-temporal memory models for image processing systems," in Proc. 12th IWSSIP, Chalkida, Greece, 2005, pp. 363-367.
-
(2005)
Proc. 12th IWSSIP
, pp. 363-367
-
-
Norell, H.1
O'Nils, M.2
-
27
-
-
26444559674
-
Optimization of memory allocation for real-time video processing on FPGA
-
Montreal, QC, Canada
-
B. Thörnberg, L. Olsson, and M. O'Nils, "Optimization of memory allocation for real-time video processing on FPGA." in Proc. 16th IEEE Int. Workshop Rapid Syst. Prototyping, Montreal, QC, Canada, 2005, pp. 141-147.
-
(2005)
Proc. 16th IEEE Int. Workshop Rapid Syst. Prototyping
, pp. 141-147
-
-
Thörnberg, B.1
Olsson, L.2
O'Nils, M.3
-
28
-
-
33746903967
-
Address generation for FPGA RAMs for efficient implementation of real-time video processing systems
-
Tampere, Finland
-
N. Lawal, B. Thörnberg, and M. O'Nils, "Address generation for FPGA RAMs for efficient implementation of real-time video processing systems," in Proc. Conf. Field Program. Logic and Appl., Tampere, Finland, 2005, pp. 136-141.
-
(2005)
Proc. Conf. Field Program. Logic and Appl
, pp. 136-141
-
-
Lawal, N.1
Thörnberg, B.2
O'Nils, M.3
-
29
-
-
0038105324
-
Data dependency size estimation for use in memory optimization
-
Jul
-
P. G. Kjeldsberg, F. Catthoor, and E. J. Aas, "Data dependency size estimation for use in memory optimization," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 22, no. 7, pp. 908-921, Jul. 2003.
-
(2003)
IEEE Trans. Comput.-Aided Design Integr. Circuits Syst
, vol.22
, Issue.7
, pp. 908-921
-
-
Kjeldsberg, P.G.1
Catthoor, F.2
Aas, E.J.3
-
30
-
-
47849126837
-
Multidimensional incremental loop fusion for data locality
-
The Hague, The Netherlands
-
S. Verdoolaege, M. Braynooghe, G. Janssens, and F. Catthoor, "Multidimensional incremental loop fusion for data locality," in Proc. IEEE Conf. Appl.-Specific Syst., Architectures, and Processors, The Hague, The Netherlands, 2003, pp. 14-24.
-
(2003)
Proc. IEEE Conf. Appl.-Specific Syst., Architectures, and Processors
, pp. 14-24
-
-
Verdoolaege, S.1
Braynooghe, M.2
Janssens, G.3
Catthoor, F.4
-
31
-
-
0032303141
-
Formalized methodology for data reuse exploration for low-power hierarchical memory mappings
-
Dec
-
S. Wuytack, J. P. Diguet, F. Catthoor, and H. De Man, "Formalized methodology for data reuse exploration for low-power hierarchical memory mappings," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 6, no. 4, pp. 529-537, Dec. 1998.
-
(1998)
IEEE Trans. Very Large Scale Integr. (VLSI) Syst
, vol.6
, Issue.4
, pp. 529-537
-
-
Wuytack, S.1
Diguet, J.P.2
Catthoor, F.3
De Man, H.4
-
32
-
-
26444597606
-
Design of real-time signal processing ASIC for noise reduction in moving video images
-
B. Oelmann, H. Norell, R. Andersson, and Y. Xu, "Design of real-time signal processing ASIC for noise reduction in moving video images," in Proc. IEEE Norchip Conf., 1999, pp. 228-233.
-
(1999)
Proc. IEEE Norchip Conf
, pp. 228-233
-
-
Oelmann, B.1
Norell, H.2
Andersson, R.3
Xu, Y.4
-
34
-
-
33947579192
-
Optimization Modeling With Lingo
-
L. Schrage, Optimization Modeling With Lingo. Lindo Syst., 1999.
-
(1999)
Lindo Syst
-
-
Schrage, L.1
-
38
-
-
0036715137
-
Smart cameras as embedded systems
-
Sep
-
W. Wolf, B. Ozer, and T. Lv, "Smart cameras as embedded systems," Computer, vol. 35, no. 9, pp. 48-53, Sep. 2002.
-
(2002)
Computer
, vol.35
, Issue.9
, pp. 48-53
-
-
Wolf, W.1
Ozer, B.2
Lv, T.3
-
39
-
-
7444268120
-
Video processing for early stage maize plant detection
-
D. S. Shrestha, B. L. Steward, and S. J. Birrell, "Video processing for early stage maize plant detection," Biosyst. Eng., vol. 89, no. 2, pp. 119-129, 2004.
-
(2004)
Biosyst. Eng
, vol.89
, Issue.2
, pp. 119-129
-
-
Shrestha, D.S.1
Steward, B.L.2
Birrell, S.J.3
-
40
-
-
85032751331
-
Active video-based surveillance system: The low-level image and video processing techniques needed for implementation
-
Mar
-
G. L. Foresti et al., "Active video-based surveillance system: The low-level image and video processing techniques needed for implementation," IEEE Signal Process. Mag., vol. 22, no. 2, pp. 25-37, Mar. 2005.
-
(2005)
IEEE Signal Process. Mag
, vol.22
, Issue.2
, pp. 25-37
-
-
Foresti, G.L.1
-
41
-
-
34047167028
-
Impact of bit-width specification on the memory hierarchy for a real-time video processing system
-
Munich, Germany
-
B. Thörnberg and M. O'Nils, "Impact of bit-width specification on the memory hierarchy for a real-time video processing system," in Proc. DATE, Munich, Germany, 2006, pp. 1-2.
-
(2006)
Proc. DATE
, pp. 1-2
-
-
Thörnberg, B.1
O'Nils, M.2
-
42
-
-
33947604204
-
Oct.). Feasibility of incremental translation. Katholieke Univ. Leuven, Heverlee, Belgium
-
Report CW348, Online, Available
-
S. Verdoolaege, F. Catthoor, M. Braynooghe and G. Janssens. (2002, Oct.). Feasibility of incremental translation. Katholieke Univ. Leuven, Heverlee, Belgium, Report CW348. [Online], Available: http://www.cs.kuleuven.be/ publicaties/rapporten/CW/2002/
-
(2002)
-
-
Verdoolaege, S.1
Catthoor, F.2
Braynooghe, M.3
Janssens, G.4
|