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Volumn 26, Issue 4, 2007, Pages 781-800

Bit-width constrained memory hierarchy optimization for real-time video systems

Author keywords

Bit width; Memory hierarchy; Polyhedral; Video

Indexed keywords

COLOR IMAGE PROCESSING; INTEGER PROGRAMMING; NONLINEAR PROGRAMMING; REAL TIME CONTROL; VIDEO SIGNAL PROCESSING;

EID: 33947595234     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2006.884569     Document Type: Article
Times cited : (3)

References (42)
  • 5
    • 13144273032 scopus 로고    scopus 로고
    • Quality-driven design by bit-width optimization for video applications
    • Kitakyushu, Japan
    • Y. Cao and H. Yasuura, "Quality-driven design by bit-width optimization for video applications," in Proc. Conf. Asia and South Pacific Des. Autom., Kitakyushu, Japan, 2003, pp. 532-537.
    • (2003) Proc. Conf. Asia and South Pacific Des. Autom , pp. 532-537
    • Cao, Y.1    Yasuura, H.2
  • 7
    • 32544453450 scopus 로고    scopus 로고
    • IMEM: An object-oriented memory- and interface modelling approach for realime video systems
    • Marseille, France, CD-ROM
    • B. Thörnberg, H. Norell, and M. O'Nils, "IMEM: An object-oriented memory- and interface modelling approach for realime video systems," in Proc. Forum Specification and Des. Lang., Marseille, France, 2002. [CD-ROM].
    • (2002) Proc. Forum Specification and Des. Lang
    • Thörnberg, B.1    Norell, H.2    O'Nils, M.3
  • 9
    • 0034795611 scopus 로고    scopus 로고
    • SystemC - A modelling platform supporting multiple design abstractions
    • Montreal, QC, Canada
    • P. R. Panda, "SystemC - A modelling platform supporting multiple design abstractions," in Proc. 14th Int. Svmp. Syst. Synth., Montreal, QC, Canada, 2001, pp. 75-80.
    • (2001) Proc. 14th Int. Svmp. Syst. Synth , pp. 75-80
    • Panda, P.R.1
  • 12
    • 32544459769 scopus 로고    scopus 로고
    • Polyhedral space generation and memory estimation from interface and memory nodels of real-time video systems
    • B. Thörnberg, Q. Hu, M. Palkovic, M. O'Nils, and P. G Kjeldsberg, "Polyhedral space generation and memory estimation from interface and memory nodels of real-time video systems," J. Syst. Softw., vol. 79, no. 2, pp. 231-245, 2005.
    • (2005) J. Syst. Softw , vol.79 , Issue.2 , pp. 231-245
    • Thörnberg, B.1    Hu, Q.2    Palkovic, M.3    O'Nils, M.4    Kjeldsberg, P.G.5
  • 13
    • 2942564431 scopus 로고    scopus 로고
    • Storage requirement estimation for optimized design of data intensive applications
    • P. G. Kjeldsberg, F. Catthoor, and E. J. Aas, "Storage requirement estimation for optimized design of data intensive applications," ACM Trans. Des. Autom. Electron. Syst., vol. 1, no. 2, pp. 133-158, 2004.
    • (2004) ACM Trans. Des. Autom. Electron. Syst , vol.1 , Issue.2 , pp. 133-158
    • Kjeldsberg, P.G.1    Catthoor, F.2    Aas, E.J.3
  • 14
    • 0031674736 scopus 로고    scopus 로고
    • System-level data-flow transformation exploration and power-area trade-offs demonstrated on video codecs
    • F. Catthoor et al., "System-level data-flow transformation exploration and power-area trade-offs demonstrated on video codecs," J. VLSI Signal Process. Syst. Signal Image Video Technol., vol. 18, no. 1, pp. 39-50, 1998.
    • (1998) J. VLSI Signal Process. Syst. Signal Image Video Technol , vol.18 , Issue.1 , pp. 39-50
    • Catthoor, F.1
  • 16
    • 0030286417 scopus 로고    scopus 로고
    • Achieving full parallelism using multidimensional retiming
    • Nov
    • N. Passos and E. Sha, "Achieving full parallelism using multidimensional retiming," IEEE Trans. Parallel Distrib. Syst., vol. 7, no. 11, pp. 1150-1163, Nov. 1996.
    • (1996) IEEE Trans. Parallel Distrib. Syst , vol.7 , Issue.11 , pp. 1150-1163
    • Passos, N.1    Sha, E.2
  • 17
    • 0029517120 scopus 로고
    • Buffering of intermediate results in dataflow diagrams
    • Darmstadt, Germany
    • A. Woodruff and M. Stonebraker, "Buffering of intermediate results in dataflow diagrams," in Proc. 11th IEEE Int. Symp. Visual Lang., Darmstadt, Germany, 1995, pp. 187-194.
    • (1995) Proc. 11th IEEE Int. Symp. Visual Lang , pp. 187-194
    • Woodruff, A.1    Stonebraker, M.2
  • 18
    • 0030674745 scopus 로고    scopus 로고
    • Synthesis of parallel hardware implementations from synchronous dataflow graph specification
    • Pacific Grove, CA
    • M. C. Williamson and E. A. Lee, "Synthesis of parallel hardware implementations from synchronous dataflow graph specification," in Proc. Conf. Rec, 30th Asilomar Conf. Signals, Syst. and Comput., Pacific Grove, CA, 1996, pp. 1340-1343.
    • (1996) Proc. Conf. Rec, 30th Asilomar Conf. Signals, Syst. and Comput , pp. 1340-1343
    • Williamson, M.C.1    Lee, E.A.2
  • 19
    • 0032633135 scopus 로고    scopus 로고
    • Buffer memory requirements in DSP applications
    • M. Adé, R. Lawereins, and J. A. Peperstraete, "Buffer memory requirements in DSP applications," Comput. Syst. Sci. Eng., vol. 14, no. 3, pp. 155-165, 1999.
    • (1999) Comput. Syst. Sci. Eng , vol.14 , Issue.3 , pp. 155-165
    • Adé, M.1    Lawereins, R.2    Peperstraete, J.A.3
  • 20
    • 0031381304 scopus 로고    scopus 로고
    • Parameterized polyhedra and their vertices
    • V. Loechner and D. Wilde, "Parameterized polyhedra and their vertices," Int. J. Parallel Program., vol. 25, no. 6, pp. 525-549, 1997.
    • (1997) Int. J. Parallel Program , vol.25 , Issue.6 , pp. 525-549
    • Loechner, V.1    Wilde, D.2
  • 21
    • 0004005802 scopus 로고
    • A library for doing polyhedral operations,
    • M.S. thesis, Oregon State Univ, Corvallis, OR, Also published in IRISA technical report PI Rennes, France
    • D. K. Wilde, "A library for doing polyhedral operations," M.S. thesis, Oregon State Univ., Corvallis, OR, 1993. Also published in IRISA technical report PI 785 Rennes, France 1993.
    • (1993) , pp. 785
    • Wilde, D.K.1
  • 22
    • 0032068586 scopus 로고    scopus 로고
    • Automatic storage management for parallel programs
    • V. Lefebrev and P. Feautrier. "Automatic storage management for parallel programs," Parallel Comput., vol. 24, no. 3/4, pp. 649-671, 1998.
    • (1998) Parallel Comput , vol.24 , Issue.3-4 , pp. 649-671
    • Lefebrev, V.1    Feautrier, P.2
  • 23
    • 0024054628 scopus 로고    scopus 로고
    • Compiler optimizations for enhancing parallelism and their impact on architecture design
    • C. Polychronopoulos, "Compiler optimizations for enhancing parallelism and their impact on architecture design," IEEE Trans. Comput., vol. 37, no. 8, pp. 991-1004, 1998.
    • (1998) IEEE Trans. Comput , vol.37 , Issue.8 , pp. 991-1004
    • Polychronopoulos, C.1
  • 24
    • 0033075413 scopus 로고    scopus 로고
    • Improving cache locality by a combination of loop and data transformations
    • Feb
    • M. Kandemir, J. Ramanujam, and A. Choudhary, "Improving cache locality by a combination of loop and data transformations," IEEE Trans. Comput., vol. 48, no. 2, pp. 159-167, Feb. 1999.
    • (1999) IEEE Trans. Comput , vol.48 , Issue.2 , pp. 159-167
    • Kandemir, M.1    Ramanujam, J.2    Choudhary, A.3
  • 25
    • 0034592553 scopus 로고    scopus 로고
    • A preprocessing step for global loop transformations for data transfer optimization
    • San Jose, CA
    • K. Danckaert, F. Catthoor, and H. De Man, "A preprocessing step for global loop transformations for data transfer optimization," in Proc. Int. Conf. CASES, San Jose, CA, 2000, pp. 34-40.
    • (2000) Proc. Int. Conf. CASES , pp. 34-40
    • Danckaert, K.1    Catthoor, F.2    De Man, H.3
  • 26
    • 33947585129 scopus 로고    scopus 로고
    • A generalized architecture for hardware synthesis of spatio-temporal memory models for image processing systems
    • Chalkida, Greece
    • H. Norell and M. O'Nils, "A generalized architecture for hardware synthesis of spatio-temporal memory models for image processing systems," in Proc. 12th IWSSIP, Chalkida, Greece, 2005, pp. 363-367.
    • (2005) Proc. 12th IWSSIP , pp. 363-367
    • Norell, H.1    O'Nils, M.2
  • 28
    • 33746903967 scopus 로고    scopus 로고
    • Address generation for FPGA RAMs for efficient implementation of real-time video processing systems
    • Tampere, Finland
    • N. Lawal, B. Thörnberg, and M. O'Nils, "Address generation for FPGA RAMs for efficient implementation of real-time video processing systems," in Proc. Conf. Field Program. Logic and Appl., Tampere, Finland, 2005, pp. 136-141.
    • (2005) Proc. Conf. Field Program. Logic and Appl , pp. 136-141
    • Lawal, N.1    Thörnberg, B.2    O'Nils, M.3
  • 31
    • 0032303141 scopus 로고    scopus 로고
    • Formalized methodology for data reuse exploration for low-power hierarchical memory mappings
    • Dec
    • S. Wuytack, J. P. Diguet, F. Catthoor, and H. De Man, "Formalized methodology for data reuse exploration for low-power hierarchical memory mappings," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 6, no. 4, pp. 529-537, Dec. 1998.
    • (1998) IEEE Trans. Very Large Scale Integr. (VLSI) Syst , vol.6 , Issue.4 , pp. 529-537
    • Wuytack, S.1    Diguet, J.P.2    Catthoor, F.3    De Man, H.4
  • 32
    • 26444597606 scopus 로고    scopus 로고
    • Design of real-time signal processing ASIC for noise reduction in moving video images
    • B. Oelmann, H. Norell, R. Andersson, and Y. Xu, "Design of real-time signal processing ASIC for noise reduction in moving video images," in Proc. IEEE Norchip Conf., 1999, pp. 228-233.
    • (1999) Proc. IEEE Norchip Conf , pp. 228-233
    • Oelmann, B.1    Norell, H.2    Andersson, R.3    Xu, Y.4
  • 34
    • 33947579192 scopus 로고    scopus 로고
    • Optimization Modeling With Lingo
    • L. Schrage, Optimization Modeling With Lingo. Lindo Syst., 1999.
    • (1999) Lindo Syst
    • Schrage, L.1
  • 38
    • 0036715137 scopus 로고    scopus 로고
    • Smart cameras as embedded systems
    • Sep
    • W. Wolf, B. Ozer, and T. Lv, "Smart cameras as embedded systems," Computer, vol. 35, no. 9, pp. 48-53, Sep. 2002.
    • (2002) Computer , vol.35 , Issue.9 , pp. 48-53
    • Wolf, W.1    Ozer, B.2    Lv, T.3
  • 39
    • 7444268120 scopus 로고    scopus 로고
    • Video processing for early stage maize plant detection
    • D. S. Shrestha, B. L. Steward, and S. J. Birrell, "Video processing for early stage maize plant detection," Biosyst. Eng., vol. 89, no. 2, pp. 119-129, 2004.
    • (2004) Biosyst. Eng , vol.89 , Issue.2 , pp. 119-129
    • Shrestha, D.S.1    Steward, B.L.2    Birrell, S.J.3
  • 40
    • 85032751331 scopus 로고    scopus 로고
    • Active video-based surveillance system: The low-level image and video processing techniques needed for implementation
    • Mar
    • G. L. Foresti et al., "Active video-based surveillance system: The low-level image and video processing techniques needed for implementation," IEEE Signal Process. Mag., vol. 22, no. 2, pp. 25-37, Mar. 2005.
    • (2005) IEEE Signal Process. Mag , vol.22 , Issue.2 , pp. 25-37
    • Foresti, G.L.1
  • 41
    • 34047167028 scopus 로고    scopus 로고
    • Impact of bit-width specification on the memory hierarchy for a real-time video processing system
    • Munich, Germany
    • B. Thörnberg and M. O'Nils, "Impact of bit-width specification on the memory hierarchy for a real-time video processing system," in Proc. DATE, Munich, Germany, 2006, pp. 1-2.
    • (2006) Proc. DATE , pp. 1-2
    • Thörnberg, B.1    O'Nils, M.2
  • 42
    • 33947604204 scopus 로고    scopus 로고
    • Oct.). Feasibility of incremental translation. Katholieke Univ. Leuven, Heverlee, Belgium
    • Report CW348, Online, Available
    • S. Verdoolaege, F. Catthoor, M. Braynooghe and G. Janssens. (2002, Oct.). Feasibility of incremental translation. Katholieke Univ. Leuven, Heverlee, Belgium, Report CW348. [Online], Available: http://www.cs.kuleuven.be/ publicaties/rapporten/CW/2002/
    • (2002)
    • Verdoolaege, S.1    Catthoor, F.2    Braynooghe, M.3    Janssens, G.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.