Compiler Optimizations for Enhancing Parallelism and Their Impact on Architecture Design

IEEE Transactions on Computers

Volumn 37, Issue 8, 1988, Pages 991-1004

  Polychronopoulos, Constantine D ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

Barrier synchronization; compilers; data dependences; hardware synchronization; loop transformations; parallel computers; parallel loops; run time dependence testing

Indexed keywords

COMPUTER SYSTEMS, DIGITAL -- PARALLEL PROCESSING;

BARRIER SYNCHRONIZATION; COMPILER OPTIMIZATIONS; CYCLE SHRINKING; LOOP TRANSFORMATIONS; PARALLEL PROGRAMS;

COMPUTER ARCHITECTURE;

EID: 0024054628     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.2249     Document Type: Article

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