Bias voltage controlled memory effect in in-plane quantum-wire transistors with embedded quantum dots

IEEE Electron Device Letters

Volumn 27, Issue 12, 2006, Pages 955-958

  Muller, Christian M ^a   Worschech, L ^a   Schliemann, A ^a,b   Forchel, A ^a  

^a UNIVERSITY OF WÜRZBURG   (Germany)

^b QIMONDA DRESDEN GMBH AND CO OHG   (Germany)

Author keywords

Floating gate; Quantum dot (QD); Quantum wire transistor (QWT); Threshold hysteresis

Indexed keywords

BIAS VOLTAGE; DRAIN CURRENT; HYSTERESIS; SEMICONDUCTING ALUMINUM COMPOUNDS; SEMICONDUCTING GALLIUM ARSENIDE; SEMICONDUCTOR QUANTUM DOTS; SEMICONDUCTOR QUANTUM WIRES; VOLTAGE CONTROL;

EMBEDDED QUANTUM DOTS; FLOATING GATE; QUANTUM-WIRE TRANSISTORS; THRESHOLD HYSTERESIS;

TRANSISTORS;

EID: 33947225545     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2006.886325     Document Type: Article

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