메뉴 건너뛰기




Volumn 2005, Issue , 2005, Pages 493-496

Source/drain germanium condensation for P-channel strained ultra-thin body transistors

Author keywords

[No Author keywords available]

Indexed keywords

EPITAXIAL GROWTH; GERMANIUM; MOSFET DEVICES; SILICON; SILICON ON INSULATOR TECHNOLOGY;

EID: 33847757117     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (11)

References (8)
  • 1
    • 3242671509 scopus 로고    scopus 로고
    • A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors
    • T. Ghani et al., "A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors," IEDM Tech. Dig., pp. 978, 2003.
    • (2003) IEDM Tech. Dig , pp. 978
    • Ghani, T.1
  • 2
    • 27744475710 scopus 로고    scopus 로고
    • Embedded SiGe S/D PMOS on thin body SOI substrate with drive current enhancement
    • D. Zhang et al., "Embedded SiGe S/D PMOS on thin body SOI substrate with drive current enhancement," Symp. VLSI Tech., pp. 26, 2005.
    • (2005) Symp. VLSI Tech , pp. 26
    • Zhang, D.1
  • 3
    • 19744383008 scopus 로고    scopus 로고
    • Finite-element study of strain distribution in transistor with silicon-germanium source and drain regions
    • Y.-C. Yeo et al., "Finite-element study of strain distribution in transistor with silicon-germanium source and drain regions," Appl. Phys. Lett., vol. 86, 023103, 2005.
    • (2005) Appl. Phys. Lett , vol.86 , pp. 023103
    • Yeo, Y.-C.1
  • 4
    • 0842288292 scopus 로고    scopus 로고
    • Process-strained silicon (PSS) CMOS Technology featuring 3D strain engineering
    • C.-H. Ge et al., "Process-strained silicon (PSS) CMOS Technology featuring 3D strain engineering," IEDM Tech. Dig., pp. 73, 2003.
    • (2003) IEDM Tech. Dig , pp. 73
    • Ge, C.-H.1
  • 5
    • 0036045607 scopus 로고    scopus 로고
    • High-performance strained Si-on-insulator MOSFETs by novel fabrication processes utilizing Ge-condensation technique
    • T. Tezuka et al., "High-performance strained Si-on-insulator MOSFETs by novel fabrication processes utilizing Ge-condensation technique," Symp. VLSI Tech., pp. 96, 2002.
    • (2002) Symp. VLSI Tech , pp. 96
    • Tezuka, T.1
  • 6
    • 0035691472 scopus 로고    scopus 로고
    • A simple and efficient model for quantization effects of hole inversion layer in MOS devices
    • Y.-T. Hou et al., "A simple and efficient model for quantization effects of hole inversion layer in MOS devices," IEEE Trans. Electron Dev., vol. 48, pp. 2893, 2001
    • (2001) IEEE Trans. Electron Dev , vol.48 , pp. 2893
    • Hou, Y.-T.1
  • 7
    • 17044429048 scopus 로고    scopus 로고
    • Lattice strain analysis of transistor structures with SiGe and SiC source/drain Stressors
    • K.-W. Ang et al., "Lattice strain analysis of transistor structures with SiGe and SiC source/drain Stressors," Appl. Phys. Lett., vol. 86, 093102, 2005.
    • (2005) Appl. Phys. Lett , vol.86 , pp. 093102
    • Ang, K.-W.1
  • 8
    • 0344066269 scopus 로고    scopus 로고
    • Oxidation rate enhancement of SiGe epitaxial films oxidized in dry ambient
    • M. Spadafora et al., "Oxidation rate enhancement of SiGe epitaxial films oxidized in dry ambient," Appl. Phys. Lett., vol. 83, pp. 3714, 2003.
    • (2003) Appl. Phys. Lett , vol.83 , pp. 3714
    • Spadafora, M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.