A robust power gating structure and power mode transition strategy for MTCMOS design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 15, Issue 1, 2007, Pages 80-89

  Abdollahi, Afshin ^b   Fallah, Farzan ^b   Pedram, Massoud ^a,b  

^a IEEE

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Ground bounce; Leakage; Multithreshold CMOS (MTCMOS); Power gating; Power mode transition

Indexed keywords

ELECTRIC DISCHARGES; ELECTRIC NETWORK ANALYSIS; LEAKAGE CURRENTS; LOGIC GATES; SHORT CIRCUIT CURRENTS; THRESHOLD LOGIC;

GROUND BOUNCE; MULTITHRESHOLD CMOS (MTCMOS); POWER GATING; POWER MODE TRANSITION; THRESHOLD LEVELS;

CMOS INTEGRATED CIRCUITS;

EID: 33847724809     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2007.891093     Document Type: Article

References (14)

1. S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, "l-V power supply high-speed digital circuit technology with multithreshold CMOS," IEEE J. Solid-State Circuits, vol. 30, no. 8, pp. 847-854, Aug. 1995.
2. J. Kao and A. P. Chandrakasan, "Dual-threshold voltage techniques for low-power digital circuits," IEEE J. Solid-State Circuits, vol. 35, no. 7, pp. 1009-1018, Jul. 2000.
3. A. Abdollahi, F. Fallah, and M. Pedram, "An effective power mode transition technique in MTCMOS circuits," in Proc. Design Autom. Conf., 2005, pp. 37-42.
4. J. Kao, A. Chandrakasan, and D. Antoniadis, "Transistor sizing issues and tool for multi-threshold CMOS technology," in Proc. Design Autom. Conf., 1997, pp. 409-414.
5. J. Kao, S. Narenda, and A. Chandrakasan, "MTCMOS hierarchical sizing based on mutual exclusive discharge patterns," in Proc. Design Autom. Conf., 1998, pp. 495-500.
6. M. Anis, S. Areibi, M. Mahmoud, and M. Elmasry, "Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique," in Proc. Design Autom. Conf., 2002, pp. 480-485.
7. S. Kim, S. V. Kosonocky, D. R. Knebel, and K. Stawiasz, "Experimental measurement of a novel power gating structure with intermediate power saving mode," in Proc. Int. Symp. Low Power Electron. Design, 2004, pp. 20-25.
8. S. Kim, S. V. Kosonocky, Stephen, and D. R. Knebel, "Understanding and minimizing ground bounce during mode transition of power gating structures," in Proc. Int. Symp. Low Power Electron. Design, 2003, pp. 22-25.
9. A. Abdollahi, F. Fallah, and M. Pedram, "Leakage current reduction in CMOS VLSI circuits by input vector control," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 2, pp. 140-154, Feb. 2004.
10. H.-S. Won et al., "An MTCMOS design methodology and its application to mobile computing," in Proc. Int. Symp. Low Power Electron. Design, 2003, pp. 110-115.
11. Usami et al., "Automated selective multi-threshold design for ultra-low standby applications," in Proc. Int. Symp. Low Power Electron. Design, 2002, pp. 202-206.
12. M. Johnson, D. Somasekhar, and K. Roy, "Leakage control with efficient use of transistor stacks in single threshold CMOS," in Proc. Design Autom. Conf., 1999, pp. 442-445.
13. T. Cormen, C. Leiserson, R. Rivest, and C. Stein, Introduction to Algorithms, 2nd ed. Cambridge, MA: MIT Press, 2001.
14. G. De Micheli, Synthesis and Optimization of Digital Circuits. New York: McGraw-Hill, 1994.